Asynchronous Data Recovery Circuit Using Pulse Width Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed asynchronous interfaces face complexity and high power consumption due to multiple clock phases, phase imbalance, and dependency on phase relationships, limiting data frame size and increasing power usage even after phase selection.
Innovation Solution
A low-power architecture for data recovery that asynchronously detects data bits using a pulse width indicator circuit with unbalanced inverters, eliminating the need for multiple phase clock generation and oversampling, and synchronously storing data in a temporary storage before transferring it to a synchronous domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple clock phases are used for data recovery, then data sampling accuracy is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent extracts only the necessary function of clock phase generation by using a single clock phase with adjustable delay instead of generating multiple clock phases. This eliminates the power consumption associated with generating and maintaining multiple clock phases while retaining the essential sampling function through the adjustable delay element.
Solution Approach 2:
The patent introduces dynamic adjustability to the delay element, allowing the sampling point to be dynamically optimized for different data rates and conditions. This dynamic adjustment replaces the static multiple-phase approach, enabling accurate sampling with a single clock phase and reducing power consumption.
2Measurement precision
If multiple clock phases are used for data recovery, then data sampling accuracy is improved, but device complexity increases
Solution Approach 1:
The patent removes the complex multiple-phase clock generation infrastructure and retains only the essential sampling function through a single clock phase with adjustable delay. This extraction simplifies the device architecture while maintaining sampling accuracy.
Solution Approach 2:
The patent changes the approach from varying clock phase to varying delay time. By adjusting the delay parameter of a single clock phase rather than switching between multiple phases, the system achieves the same sampling accuracy with significantly reduced complexity.
3Measurement precision
If DLL is used for phase generation, then clock phase accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces the expensive and power-hungry DLL with a simpler, lower-cost delay element that achieves sufficient accuracy without the complex feedback mechanisms of a DLL. This substitution reduces power consumption while maintaining adequate clock phase accuracy for data sampling.
4Productivity
If interface toggles at twice data rate, then data recovery capability is improved, but power consumption increases
Solution Approach 1:
The patent introduces dynamic delay adjustment that allows the sampling point to be optimized for the actual data rate and conditions. This dynamic adjustment enables accurate data recovery without requiring the interface to toggle at twice the data rate, thereby reducing power consumption while maintaining recovery capability.
Data Source
AI summary
A data recovery circuit includes a pulse width indicator circuit, an edge detection circuit and a first storage. The pulse width indicator circuit is configured to receive, at an input, a data stream and provide pulses, at respective outputs, that are indicative of respective data bits in the received data stream. The edge detection circuit is configured to receive, on respective inputs, the pulses from the pulse width indicator circuit and provide respective storage signals, on respective outputs that are indicative of a logic level of the respective data bits, responsive to the pulses. The first storage is configured to receive and store the respective storage signals.