Asynchronous Data Sampling Controller for Memory Clock Phase Decoupling
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Solution Overview
Problem
Conventional data sampling devices for memory chips face reliability issues due to phase differences in clock signals caused by delays, which can be exacerbated by temperature variations and electromagnetic interference, leading to inaccurate data sampling.
Innovation Solution
A data sampling device with an asynchronous data memory that stores sampling data independently using a writing clock and reads it using a reading clock, where the writing and reading operations are decoupled, allowing for accurate data sampling even with significant delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronized data sampling is used with pre-estimated phase differences, then data sampling accuracy is maintained under normal conditions, but reliability deteriorates under temperature variations and electromagnetic interference
Solution Approach 1:
The patent transitions from a static synchronized sampling system with fixed phase differences to a dynamic asynchronous system where writing and reading operations can occur at different times. The asynchronous data memory allows the system to adapt to varying delay conditions caused by temperature and electromagnetic interference, maintaining reliability without requiring precise phase matching.
Solution Approach 2:
The patent introduces an asynchronous data memory as an intermediary buffer between the sampling operation and the read operation. This intermediary component decouples the writing clock and reading clock, allowing each to operate independently without being constrained by phase synchronization requirements, thus resolving the contradiction between accuracy and reliability.
2Measurement precision
If synchronized sampling with phase difference compensation is implemented, then sampling accuracy is improved under normal conditions, but device complexity increases to handle delay variations
Solution Approach 1:
The patent extracts the phase synchronization requirement from the sampling system by using an asynchronous data memory. The writing operation and reading operation are separated into different time domains, eliminating the need for complex phase difference calculation and compensation logic while maintaining sampling accuracy.
3Reliability
If asynchronous data memory with independent writing and reading clocks is used, then reliability under temperature variations is improved, but device complexity increases
Solution Approach 1:
The patent changes the temporal parameter relationship between writing and reading operations from synchronized (fixed phase difference) to asynchronous (independent timing). This parameter change allows the system to tolerate delay variations caused by temperature and electromagnetic interference without requiring complex compensation mechanisms, as the asynchronous memory naturally accommodates timing differences.
Data Source
AI summary
Designs of a sampling controller working with memory chips are described. The designs enable a memory chip to work in high frequency clocks, resulting in high data throughput rate. A data sampling device includes a memory chip and a sampling controller. The sampling controller includes an asynchronous data memory. A data writing port of the asynchronous data memory receives a clock signal and employs the clock signal as a writing clock to store the sampling data into an internal memory and activate a data reading port thereof to read and output the sampling data.