Asynchronous Data Transmission Synchronization Across Clock Domains
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Solution Overview
Problem
Data transmission between devices with different clock frequencies faces challenges in meeting the integral and differential error criteria due to asynchronous transitions, leading to inaccuracies and noise interpretation.
Innovation Solution
A method and device that generate a second total increment by extrapolation or interpolation of the first total increment, with a delay between polling and transmission, to synchronize data across different frequencies, ensuring compliance with the integral error criterion while improving the differential error criterion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is accumulated over an integer number of data path clock cycles to meet the integral error criterion, then all partial increments are fully transmitted, but the number of partial increments fluctuates between N and N+1 causing beat frequency effects and additional noise in the read unit
Solution Approach 1:
The patent applies preliminary action by calculating and storing the nominal number of data path clock cycles (ndc) in advance based on the ratio of data path clock frequency to query clock frequency. This pre-calculated nominal value serves as a reference for subsequent adjustments, allowing the system to proactively compensate for frequency variations rather than reactively adjusting after beat frequency effects have already introduced noise.
Solution Approach 2:
The patent changes the parameter of the number of data path clock cycles from a fixed integer to a dynamically adjustable value. By modifying the number of data path clock cycles based on the difference between the actual accumulated cycles and the nominal value, the system adapts to frequency variations and eliminates the fluctuation between N and N+1 cycles that causes beat frequency effects.
2Ease of operation
If the query clock cycle is set as an integer multiple of the data path clock cycle to simplify synchronization, then clock alignment is improved, but slightest frequency deviations still lead to beat frequency effects and inadequate fulfillment of the differential error criterion
Solution Approach 1:
The system performs preliminary calculation of the nominal number of data path clock cycles based on the integer multiple relationship between query clock and data path clock. This pre-established nominal value serves as a baseline that guides real-time adjustments, allowing the system to maintain the simplicity of integer multiple synchronization while compensating for frequency deviations through dynamic adjustment of the actual cycle count.
Solution Approach 2:
The patent introduces dynamics by making the number of data path clock cycles adjustable rather than fixed. Even though the query clock cycle is set as an integer multiple of the data path clock cycle for ease of synchronization, the system dynamically modifies the actual number of data path clock cycles used in each accumulation period based on frequency variations, thereby maintaining precision despite the simplified synchronization approach.
3Measurement precision
If the number of data path clock cycles is adjusted to compensate for frequency variations, then the differential error criterion is improved, but the complexity of determining the correct number of cycles increases
Solution Approach 1:
The patent implements feedback by continuously monitoring the actual number of data path clock cycles accumulated during each query clock period and comparing it with the pre-calculated nominal value. The difference (deviation) is fed back to adjust the number of cycles for the next accumulation period, creating a closed-loop control system that automatically corrects for frequency variations without requiring complex external control mechanisms.
Solution Approach 2:
The system applies self-service by using its own internal measurements of actual clock cycle accumulation to automatically adjust its operation. The read unit monitors its own query clock timing and the associated data path clock cycles, calculates the deviation from the nominal value, and self-corrects by adjusting the number of cycles in subsequent periods, eliminating the need for external synchronization control.
Data Source
Figure 1A~1B
Figure 2
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AI summary
The invention relates to a method for transmitting data between a first unit which accumulates data that has been generated with a first frequency and a second unit which requests the accumulated data with a second frequency. The method has the steps of requesting a first total increment and a first value, which represents a time increment belonging to the first total increment, from the first unit, said first total increment being the data content of the accumulated data block provided at the request time in the first unit; generating a second total increment from the first total increment using the first value, the second total increment being the data content of a data block adapted to a nominal time increment of the second frequency; and transmitting the second total increment to the second unit.