Asynchronous Dataflow Circuit Fabric From Synchronous Logic
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Solution Overview
Problem
The industry faces challenges in effectively converting synchronous circuit designs to asynchronous designs due to the complexity of interconnect architecture required for asynchronous token verification protocols, leading to performance issues in scaling and redesign flaws.
Innovation Solution
A method and system for automatically converting synchronous architectures into asynchronous dataflow implementations, preserving logical primitives and using programmable switch points and tracks to communicate data and protocol signals between logic blocks, allowing for the same synthesis algorithms to be used without redesign, and enabling conversion of synchronous circuits to asynchronous circuits with improved interconnect methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous circuit designs are converted to asynchronous designs using traditional interconnect architecture, then functional equivalence is maintained, but device complexity and performance scaling are worsened due to the complexity of interconnect architecture required for asynchronous token verification protocols
Solution Approach 1:
The patent creates a simplified copy of the asynchronous verification protocol functionality by implementing completion detection circuits within logic blocks that replicate the essential handshake behavior without requiring complex interconnect architecture. This allows asynchronous operation to be emulated using the existing synchronous interconnect fabric, thereby maintaining functional equivalence while avoiding the complexity of redesigning the entire interconnect system for asynchronous protocols.
2Reliability
If synchronous circuit designs are converted to asynchronous designs using traditional interconnect architecture, then functional equivalence is maintained, but productivity and performance are worsened due to scaling issues
Solution Approach 1:
The patent enables logic blocks to perform their own asynchronous verification functions through integrated completion detection circuits. Each logic block independently detects when its inputs are complete and generates appropriate handshake signals, eliminating the need for complex centralized interconnect verification architecture. This self-service approach allows asynchronous operation to scale efficiently with the existing synchronous interconnect fabric, improving productivity and performance scaling.
3Productivity
If synchronous circuit designs are converted to asynchronous designs, then increased parallelism and performance are achieved, but device complexity increases due to redesign requirements
Solution Approach 1:
The patent makes the synchronous interconnect fabric universal by enabling it to support both synchronous and asynchronous operation modes through the addition of completion detection circuits. The same interconnect architecture that originally supported synchronous clocked operation now also supports asynchronous token-based operation, eliminating the need for separate complex asynchronous interconnect systems. This multi-functionality allows designers to achieve increased parallelism and performance while avoiding the device complexity of complete redesign.
Data Source
AI summary
Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and repeatable process for evaluating synchronous circuit designs, converting the wires, switches/connections and logic functions to equivalent-function asynchronous circuit designs and hence implementing a functionally equivalent asynchronous circuit with all the benefits thereof. Further provided are a process for systematically doing the conversion and hardware equivalents (in form or functional description) for the asynchronous components. Using the present invention, any synchronous circuit design can be converted to an asynchronous equivalent, typically with no change to the original design implementation.