Asynchronous DDR Controller Reads and Writes for Lower DRAM Latency
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Solution Overview
Problem
Existing DDR controllers experience inefficiencies in WRITE operations due to cache disturbances and high latency in READ operations, particularly in applications like image processing and machine learning, where filling memory locations with zeros or fixed patterns leads to unnecessary READs and prolonged preparation times, consuming 70% of the total READ time.
Innovation Solution
Implementing asynchronous READ/WRITE operations in DDR controllers through async memget and async memset functions, allowing the computing device to transmit commands independently and enabling the DDR controller to trigger memory access requests without blocking other operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If synchronous READ operations are used in DDR controllers, then data can be accessed from DRAM, but the computing device is blocked during the READ process resulting in high latency
Solution Approach 1:
The patent implements asynchronous READ operations where the computing device can issue READ commands to the DDR controller and immediately proceed with other tasks. The DDR controller independently manages the READ operation sequence (pre-charge, row-activation, column-access) in the background, allowing preliminary actions to be initiated without blocking the main processing flow.
Solution Approach 2:
The patent separates the READ operation into two independent parts: (1) command issuance by the computing device, and (2) execution by the DDR controller. This segmentation allows the computing device to issue multiple READ commands in parallel without waiting for each operation to complete, thereby reducing overall latency while maintaining productivity.
2Ease of manufacture
If WRITE operations fill memory locations with zero or fixed pattern, then memory can be initialized, but L2 cache is disturbed or drained resulting in unnecessary READ operations
Solution Approach 1:
The patent extracts the unnecessary READ operation from the WRITE initialization process. By implementing asynchronous WRITE operations with zero or fixed pattern filling, the system can initialize memory directly without first reading existing cache data, thereby eliminating the harmful sequence of READ-WRITE-WRITEBACK that disturbs L2 cache.
Solution Approach 2:
The patent converts the potential harm of cache disturbance into a benefit by using asynchronous operations. Instead of synchronously reading and rewriting cache lines (which causes cache pollution), the system performs asynchronous writes that allow the cache to be updated in the background without blocking or disturbing the main processing flow.
3Measurement precision
If traditional READ operation sequence is used (pre-charge, row-activation, column-access), then data can be accessed from DRAM, but 70% of time is lost in preparation commands
Solution Approach 1:
The patent applies preliminary action by having the DDR controller prepare and queue the necessary command sequence (pre-charge, row-activation, column-access) in advance. The controller independently manages this preparation timeline without blocking the computing device, allowing the actual data access to occur with minimal perceived delay.
Solution Approach 2:
The patent introduces dynamic command queuing and scheduling in the DDR controller. Instead of a rigid synchronous sequence, the controller dynamically manages the preparation commands based on available bandwidth and current operations, optimizing the timing of pre-charge, row-activation, and column-access commands to minimize overall preparation time while ensuring data access accuracy.
Data Source
AI summary
A system and method for implementing asynchronous READ/WRITE operations in a Double Data Rate (DDR) controller to reduce Dynamic Random Access Memory (DRAM) access latency. The system provides a program configurable interface to the DDR controller for pre-fetching data from a memory address of interest into cache, for serving an asynchronous READ operation. The asynchronous READ operation minimizes or reduces pre-charge latency, Row Address Select (RAS) latency, and Column Address Select (CAS) latency. The system provides a program configurable interface to the DDR controller the read operation or the write operation being for providing buffer data directly to the DDR controller to handle an asynchronous WRITE operation.