Asynchronous Digital LDO for Fast Voltage Regulation
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Solution Overview
Problem
Traditional digital low-dropout regulator circuits are limited by system clock speed, making it difficult to rapidly respond to changes in load current and regulate output voltage effectively.
Innovation Solution
A digital low-dropout regulator that uses an asynchronous clock generation circuit to produce a reference clock signal with a higher frequency than the system clock signal, allowing for rapid voltage regulation by updating the switch control signal based on this reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the system clock speed is increased to improve voltage regulation speed, then the voltage regulation speed is improved, but the power consumption of the overall device increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where the regulator circuit can operate at different clock frequencies depending on the regulation needs. The system uses a first clock frequency for normal operation and a second, higher clock frequency when rapid regulation is required, allowing the voltage regulation speed to be improved temporarily without continuously increasing power consumption.
Solution Approach 2:
The patent employs periodic high-frequency clock cycles interspersed with lower-frequency operation. The controller circuit activates the higher clock frequency periodically when voltage regulation demands arise, rather than maintaining high frequency continuously, thus achieving fast regulation when needed while minimizing overall power consumption during stable operation.
2Use of energy by moving object
If the system clock speed is kept low to reduce power consumption, then the power consumption is reduced, but the voltage regulation speed becomes limited
Solution Approach 1:
The system dynamically adjusts the clock frequency based on real-time regulation demands. During normal stable operation, the regulator runs at a lower clock frequency to minimize power consumption. When voltage changes require rapid response, the controller switches to a higher clock frequency, ensuring fast regulation speed is available on-demand without paying the power consumption penalty continuously.
Solution Approach 2:
The patent changes the clock frequency parameter adaptively based on the operating conditions. The controller circuit monitors the voltage regulation state and adjusts the clock frequency parameter between two levels: a lower frequency for energy efficiency during stable states, and a higher frequency for rapid response when voltage adjustments are needed, thus optimizing the trade-off between power consumption and regulation speed.
Data Source
AI summary
The present disclosure provides a digital low-dropout regulator (DLDO) and an electronic device using the same. The DLDO includes a voltage comparator circuit, a switch control circuit, a power switch module, and an asynchronous clock generation circuit. The voltage comparator circuit compares a reference voltage with the output voltage to output a comparison result signal. The switch control circuit generates a switch control signal based on the comparison result signal. The power switch module is controlled by the switch control signal to switch between the on state and the off state, thereby adjusting the output voltage. The asynchronous clock generation circuit generates a reference clock signal that is asynchronous with the system clock signal used in the load circuit and has a higher clock frequency. This allows the switch control circuit to update the switch control signal based on the reference clock signal.