Asynchronous Divider Phasing Detection in CDR Clock Domains
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In clock and data recovery (CDR) systems, the lack of a mechanism to detect and correct the relative phasing of asynchronous dividers leads to improper shifting of deserialized bits between the data sampling clock domain and the edge sampling clock domain, causing operational issues.
Innovation Solution
A CDR system incorporating an asynchronous clock phasing detection circuit that includes a first divider, a second divider, a quantization and logic circuit, an oscillator, and a control circuit to generate a detection signal indicating the relative phase difference between the divided clock signals, allowing for correction mechanisms such as polarity inversion of the dividers to achieve proper phasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous dividers are used to divide clock signals in different domains, then the CDR system can achieve deserialization and retiming functions, but the relative phasing between divided clock signals becomes unpredictable causing improper shifting of deserialized bits
Solution Approach 1:
The patent implements a feedback mechanism by detecting the relative phasing between divided clock signals from different asynchronous dividers and using this detection to control the dividers. The phasing detection circuit monitors the phase relationship and feeds this information back to adjust the divider operation, ensuring proper alignment of deserialized bits between clock domains.
Solution Approach 2:
The patent introduces a phasing detection circuit as an intermediary component between the asynchronous dividers and the deserialization/retiming functions. This intermediary detects and reports the relative phasing information, enabling the system to bridge the phase uncertainty gap between different clock domains without direct coupling.
2Device complexity
If no phasing detection mechanism is implemented, then the device complexity is reduced, but improper phasing causes operational failures in the CDR system
Solution Approach 1:
The patent enables the CDR system to self-diagnose and self-correct phasing issues through the phasing detection circuit. The system automatically detects relative phasing between divided clock signals and uses this information to control the dividers, eliminating the need for external calibration or manual adjustment while ensuring reliable operation.
3Ease of operation
If the relative phasing of divided clock signals is not detected and corrected, then the system operates without additional control circuits, but deserialized bits are improperly shifted between clock domains
Solution Approach 1:
The phasing detection circuit provides continuous feedback on the relative phase relationship between divided clock signals, enabling real-time correction of data shifting errors. This feedback mechanism ensures that deserialized bits are properly aligned when transferred between different clock domains, preventing information loss or corruption.
Data Source
AI summary
Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.