Asynchronous Feedback Logic RNG for High-Entropy Digital ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing hardware-based random number generators (RNGs) face challenges in generating high-speed, high-entropy random numbers due to the need for analog elements, sensitivity to environmental conditions, and reduced randomness caused by oscillator locking, making them inefficient and unreliable for digital ICs.
Innovation Solution
A digital RNG using a combinatorial logic circuit implementing an autonomous Finite-State Machine (FSM) with no fixed points, operated asynchronously, and feedback connections that ensure long cycles, producing a raw random binary sequence with enhanced randomness and pseudo-randomness properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog elements (resistors, PN-junctions) are used to generate random numbers through thermal noise and shot noise, then the quality and speed of randomness are improved, but the device becomes difficult to incorporate in digital ICs and sensitive to environmental changes
Solution Approach 1:
The patent replaces analog physical systems (thermal noise generators using resistors and shot noise generators using PN-junctions) with a digital logic-based system. The random number generator uses a linear feedback shift register (LFSR) clocked by a ring oscillator, entirely eliminating the need for analog elements while maintaining randomness generation capability through digital circuitry.
Solution Approach 2:
The patent changes the fundamental operating parameters from analog continuous signals to digital discrete signals. By using a ring oscillator to generate a clock signal that clocks an LFSR, the system operates in the digital domain with discrete binary states, improving integrability into digital ICs while maintaining the randomness function through the pseudo-random sequence generation of the LFSR.
2Productivity
If analog elements are used for random number generation, then high-speed randomness is achieved, but power consumption increases and environmental sensitivity worsens
Solution Approach 1:
The patent substitutes power-hungry analog noise-generating circuits with a digital logic implementation using a ring oscillator and LFSR. The ring oscillator generates clock signals at the required speed, and the LFSR processes these signals to produce random numbers, significantly reducing power consumption while maintaining high-speed generation capability through efficient digital logic operations.
3Device complexity
If ring oscillators are used to generate random numbers through phase jitter, then digital IC integration is improved, but oscillator locking reduces the randomness of the output sequence
Solution Approach 1:
The patent introduces an intermediary element - the linear feedback shift register (LFSR) - between the ring oscillator and the random number output. The ring oscillator generates a clock signal that clocks the LFSR, and the LFSR's internal state transitions and feedback logic process this signal to produce a pseudo-random sequence, preventing direct oscillator locking effects from degrading the randomness quality.
Solution Approach 2:
The patent employs feedback mechanisms in two forms: the ring oscillator uses feedback through its cascaded inverter structure to maintain oscillation, and the LFSR uses linear feedback from selected tap positions to generate its pseudo-random sequence. The LFSR's feedback polynomial is carefully chosen to ensure maximum period and good statistical properties, maintaining randomness quality despite the deterministic nature of the digital circuit.
Data Source
AI summary
A random binary sequence generator for generating a random binary sequence adapted to be used for producing random numbers, includes at least one logic circuit corresponding to an associated finite-state machine having a state-transition function including states arranged to form cycles of states, wherein the at least one logic circuit has a set of logic circuit inputs and a set of logic circuit outputs fed back to the logic circuit inputs; the associated finite-state machine is autonomous and asynchronous; the state-transition function is void of loops; and any of the cycles of states has either a minimum length equal to three states, in case the cycle is stable, or a minimum length of two states, in case the cycle is meta-stable.