Asynchronous Feedback Training for Data Lane Delay Alignment
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Solution Overview
Problem
The increasing data throughput in integrated circuits, where the rate of improvement in microprocessor speed exceeds memory speed, leads to timing challenges in data transmission due to variations in data lanes, making it difficult to align clock and data signals effectively, especially when a single clock is used for multiple data lanes.
Innovation Solution
An asynchronous feedback training (AFT) sequence is implemented, where a transmitter and receiver use counters to test delay settings across data lanes, with a training sequence indication and test pattern being transmitted to align the data eye, allowing for adjustments in delay settings to optimize data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock is used to latch in a data bus of multiple data lanes, then the clocking mechanism is simplified, but the speed of the data bus is limited because the clock transition must accommodate all data lanes with varying delays
Solution Approach 1:
The patent segments the data bus into multiple independent data lanes, each with its own delay setting. This allows each lane to be optimized independently for maximum speed while using a single clock source, resolving the contradiction between simplicity and speed.
Solution Approach 2:
The patent introduces dynamically adjustable delay settings for each data lane that can be modified during operation. This dynamic adjustment capability allows the system to optimize for speed by tuning each lane's delay to compensate for variations, while maintaining the simplicity of a single clock mechanism.
2Reliability
If delay settings are adjusted to accommodate the slowest data lane, then all data lanes can be clocked correctly, but the overall data transmission speed is reduced
Solution Approach 1:
The patent applies local quality by allowing each data lane to have its own specific delay setting rather than using a uniform delay for all lanes. This enables each lane to be optimized locally for maximum speed while maintaining proper alignment, resolving the contradiction between reliability and speed.
Solution Approach 2:
The patent changes the parameter of delay setting from a fixed global value to adjustable per-lane values. This parameter change allows each data lane to be tuned to its optimal delay, enabling faster transmission while maintaining reliable alignment through the AFT sequence that identifies the optimal sampling point for each lane.
3Adaptability or versatility
If the variation between data lanes is high, then individual optimization is needed, but finding a single clock edge location that works for all lanes becomes impossible
Solution Approach 1:
The patent implements feedback through the asynchronous feedback training (AFT) sequence, which monitors the quality of data reception on each lane and uses this feedback to automatically adjust delay settings. This feedback mechanism makes the system adaptable to high variation between lanes while automatically finding the optimal clock edge placement, resolving the contradiction between adaptability and ease of operation.
Solution Approach 2:
The patent enables the system to self-adjust by using the AFT sequence to automatically identify optimal delay settings for each data lane without manual intervention. The system services itself by detecting variations between lanes and autonomously optimizing each lane's timing, resolving the contradiction between adaptability and ease of operation.
Data Source
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AI summary
Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of 'N' clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.