Asynchronous FIFO Circuit for Long On-Chip Wire Latency
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Solution Overview
Problem
Long-distance on-chip communication in semiconductor chips faces significant latency due to increased resistive-capacitive delay in wires, which acts as a bottleneck in computer system performance, despite advancements in computational speed and integration density.
Innovation Solution
An asynchronous First-In-First-Out (FIFO) circuit with a data path of sequentially connected latches and a control circuit that generates control signals using GasP modules and repeaters, allowing for asynchronous signal propagation and matching latency with repeated wires, thereby facilitating efficient data transmission over long distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous control is used with clocked circuits, then data transmission can be coordinated globally, but the clock period must accommodate the maximum wire delay, limiting speed and requiring synchronization interfaces that add complexity
Solution Approach 1:
The patent extracts the clock signal generation and global synchronization mechanism from the system, replacing it with asynchronous control. Each component operates independently without a global clock, eliminating the need for synchronization interfaces and clock distribution networks while maintaining reliable data transmission through handshaking protocols.
Solution Approach 2:
The patent segments the globally synchronized system into independently controllable asynchronous components. Each component has its own control logic that operates at its optimal speed, with interfaces that negotiate timing locally rather than being constrained by a global clock period. This segmentation allows each segment to operate at maximum speed without waiting for the slowest component in the system.
2Productivity
If the forward latency of the control circuit is reduced to match the data path latency, then throughput improves, but the cycle time must accommodate the sum of forward and reverse latency, limiting operating speed
Solution Approach 1:
The patent implements dynamic latency matching where the control circuit's forward latency is made equal to the data path latency. This dynamic adjustment allows the system to operate at the maximum possible throughput without being constrained by fixed clock cycles. The asynchronous nature allows the system to adapt to varying latency conditions rather than being bound by a fixed timing regime.
Solution Approach 2:
The patent uses periodic handshaking signals to coordinate data transfer between components. Instead of continuous clocking, the system uses periodic acknowledgment and control signals that trigger data movement only when needed. This periodic action reduces the effective cycle time by eliminating idle waiting periods while maintaining proper timing coordination.
3Reliability
If repeaters are used in long wires to reduce delay, then signal strength is maintained, but the resistive-capacitive delay of the wire itself remains a bottleneck for communication speed
Solution Approach 1:
The patent introduces asynchronous control circuits as intermediaries between data components. These control circuits generate timing signals that coordinate data movement across long wires, effectively mediating the communication between producer and consumer components. The control circuits absorb the wire delay by operating asynchronously, allowing data to traverse long distances without being constrained by the wire's RC time constant.
Data Source
AI summary
The disclosed embodiments provide a first-in, first-out (FIFO) circuit that operates asynchronously. The FIFO circuit includes a data path that contains data latches sequentially connected through data-wire segments. The FIFO circuit also includes a control circuit that generates control signals for the data latches so that the data path behaves like a FIFO. The control circuit includes control components sequentially connected to each other through control-wire segments and repeaters located within the control-wire segments. The control components are configured to asynchronously generate the control signals for the data latches, and the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components.