Asynchronous Flash Memory Controller for Multi-Layer Die Management
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Solution Overview
Problem
Flash memory devices face challenges in achieving a balance between performance, capacity, and cost, particularly in multi-level cell (MLC) configurations, where endurance and performance degrade as the number of bits per cell increases.
Innovation Solution
A mass storage memory system is designed with multiple flash memory layers, each having different bit-per-cell data capacity, and a controller that manages data in parallel and asynchronously across these layers, selecting the best die for writing data based on criteria such as the shortest pending data write queue, to optimize storage flexibility and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell (MLC) flash memory is used to increase storage capacity and reduce cost, then capacity and cost are improved, but endurance and performance degrade
Solution Approach 1:
The memory system is segmented into multiple independent flash memory die, each capable of autonomous operation. The controller divides data into chunks and distributes them across multiple die for parallel writing, allowing the system to achieve high capacity while maintaining performance through parallel operations rather than sequential access to degraded MLC cells
Solution Approach 2:
The system dynamically selects which die to write to based on real-time status of each die's write queue and operational state. The controller can adaptively balance data distribution across die with varying performance characteristics, optimizing throughput while accommodating the degraded endurance of MLC cells through flexible, dynamic resource allocation
2Productivity
If synchronous parallel operations are performed across multiple flash memory die, then productivity is improved, but device complexity increases
Solution Approach 1:
Each flash memory die operates autonomously with its own internal state machine and buffer, managing its own write operations without requiring constant controller intervention. The die can independently handle data reception, processing, and storage, reducing the controller's coordination burden and simplifying the overall system architecture while maintaining parallel productivity
Solution Approach 2:
The controller is functionally segmented into multiple independent channels, each capable of managing one or more die autonomously. This channel-based architecture allows parallel data paths with minimal cross-channel coordination, reducing controller complexity while achieving high throughput through simultaneous operations across multiple segmented channels
3Adaptability or versatility
If data is written to flash memory die with different bit-per-cell capacities, then adaptability is improved, but device complexity increases
Solution Approach 1:
The controller implements a universal data management architecture that can handle multiple die types with different bit-per-cell capacities through a common interface and unified control logic. Data is managed as standardized chunks that can be distributed to any compatible die regardless of their specific capacity, providing storage flexibility without requiring complex type-specific management routines
Data Source
AI summary
A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.