Asynchronous Flipping ADC for Alias-Free Low-Power Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in ultra-low-power radio receivers due to strict antialiasing filter specifications and high power consumption, limiting multichannel capabilities and blocker robustness, especially in systems with tight power budgets like wake-up receivers.
Innovation Solution
The proposed asynchronous flipping ADC operates in continuous time, eliminating the need for antialiasing filters by encoding the integral of the input signal as a set of impulses indicating time instants where the signal crosses quantization levels, using a simplified feedback path and a single-bit digital-to-analog converter, resulting in a compact, power-efficient design with reduced electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a Nyquist ADC is used to meet strict antialiasing filter specifications, then measurement precision is improved, but power consumption increases substantially
Solution Approach 1:
The patent changes the fundamental operating parameters of the ADC by using asynchronous sampling instead of periodic sampling, and by operating in continuous time rather than discrete time. This allows the system to achieve the required SNDR without the high power consumption associated with high-speed Nyquist ADCs and their stringent antialiasing filter requirements
Solution Approach 2:
The patent employs dynamic element matching and asynchronous operation where the sampling rate and timing are dynamically adjusted based on the input signal characteristics. This dynamic approach allows the ADC to maintain high measurement precision while adapting power consumption to actual signal conditions rather than operating at fixed high power levels
2Ease of manufacture
If oversampling is used to simplify antialiasing requirements, then ease of manufacture is improved, but power consumption increases due to high sampling rate requirements
Solution Approach 1:
The asynchronous ADC dynamically adjusts its sampling rate based on the instantaneous frequency content of the input signal. When the signal is stationary or slowly varying, the sampling rate is low, reducing power consumption. When the signal changes rapidly, the sampling rate increases automatically to capture the signal details, maintaining ease of manufacture without the continuous high power consumption of fixed-rate oversampling
Solution Approach 2:
The patent uses periodic quantization levels combined with asynchronous sampling events. The quantization thresholds are fixed and periodic, simplifying the manufacturing requirements, while the sampling instants are asynchronous and event-driven, allowing the system to reduce power consumption by sampling only when necessary rather than continuously at high rates
3Measurement precision
If high sampling rate is used to achieve high SNDR, then measurement precision is improved, but device complexity increases due to substantial power overhead for ADC and subsequent processing blocks
Solution Approach 1:
The patent implements a dynamic system where the output data rate varies according to the signal characteristics. The asynchronous flipping mechanism causes the output rate to be high only when the input signal is changing rapidly, and low or zero when the signal is stationary. This dynamic behavior reduces the complexity of subsequent processing blocks compared to systems that must handle continuous high-rate data streams
Solution Approach 2:
The patent extracts only the essential signal information at the moments when it actually changes, rather than continuously sampling at high rates. By taking out only the relevant data points (when flipping occurs) and discarding redundant information (when no flipping occurs), the system achieves high SNDR with reduced device complexity in subsequent processing blocks
Data Source
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AI summary
A programmable, quantization error spectral shaping, alias-free asynchronous analog-to-digital converter (ADC) is provided. The ADC can be used for clock-less, continuous-time digital signal processing in receivers with modest Signal to Noise-plus-Distortion Ratio (SNDR) requirements and a tight power budget.