Asynchronous Clock Domain Flow Control Using Counter Comparison
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Solution Overview
Problem
System-on-chip integrated circuits face challenges with large resource consumption due to the need for numerous signal lines and first-in-first-out buffers when routing wide parallel interconnect circuitry and passing data packets across asynchronous clock domains, particularly when multiple channels and virtual channels are involved, leading to potential performance degradation and resource inefficiencies.
Innovation Solution
A communication circuitry system that uses transmitter and receiver counters to manage count values across asynchronous clock boundaries, generating a credit signal to gate data packet transmission based on available buffer space, eliminating the need for separate buffers for control signals and reducing resource consumption by comparing count values instead of passing tokens.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If first-in-first-out buffers are provided for all signals crossing the asynchronous clock boundary including token signals, then reliable data packet transmission is achieved, but circuit area and resource consumption increase significantly
Solution Approach 1:
The patent extracts the token signal from the set of signals requiring buffering, recognizing that only data packets need first-in-first-out buffering while token signals can be synchronised using simpler registration techniques. This selective approach reduces the number of buffers required across the asynchronous clock boundary.
Solution Approach 2:
The patent creates a shared first-in-first-out buffer that serves multiple channels simultaneously, allowing the same buffer resource to be reused for flow control across different data channels. This multi-functional approach significantly reduces the total buffer capacity required compared to providing separate buffers for each channel.
2Reliability
If separate first-in-first-oust buffers are provided for each channel and virtual channel, then channel isolation and reliable flow control are achieved, but device complexity and resource consumption increase
Solution Approach 1:
The patent implements a shared first-in-first-out buffer that can be accessed by multiple channels and virtual channels, allowing the same physical buffer resource to serve multiple logical channels. This reduces device complexity by eliminating the need for separate buffer structures for each channel while maintaining channel isolation through logical addressing and credit management.
Solution Approach 2:
The patent merges multiple channel-specific buffer requirements into a single shared buffer infrastructure, combining what would otherwise be multiple separate devices into one unified structure. This consolidation reduces overall device complexity while maintaining the functional separation needed for reliable flow control across different channels.
3Productivity
If wide parallel interconnect circuitry is used to connect functional circuit blocks, then high data transmission capacity is achieved, but routing distance and circuit area increase
Solution Approach 1:
The patent segments the wide parallel interconnect into multiple narrower data packet channels, breaking down the high-capacity parallel connection into several lower-capacity serial or pseudo-serial packet streams. This segmentation allows data to be transmitted across longer distances with reduced signal integrity issues while maintaining overall high throughput through time-division multiplexing.
Solution Approach 2:
The patent transitions from a spatial parallel architecture to a temporal multiplexed architecture, moving data transmission from the spatial dimension (parallel wires) to the temporal dimension (sequential packet transmission with time-division multiplexing). This dimensional change enables high data capacity over longer distances without requiring proportionally wide physical interconnects.
Data Source
AI summary
A system-on-chip integrated circuit 2 includes a packet transmitter 28 for generating data packets to be sent via a communication circuit 34 to a packet receiver 30 containing a buffer circuit 32. A transmitter counter 36 stores a transmitter count value counting data packets sent. A receiver counter 38 stores a receiver count value tracking data packets emptied from the buffer circuit 32. A comparison circuitry 40 is used to compare the transmitter count value and the receiver count value to determine whether or not there is storage space available within the buffer circuit 30 to receive transmission of further data packets. The packet transmitter 28 operates in a transmitter clock domain that is asynchronous from a receiver clock domain in which the packet receiver operates. One of the count values is passed across this asynchronous clock boundary in order that the comparison may be performed and flow control exercised.