Asynchronous Global Flags for Coprocessor Synchronization
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Solution Overview
Problem
Existing synchronization methods for coprocessors, such as neural processing units, are cumbersome and introduce latency due to software interrupts, especially when a control CPU is running a full operating system, making it difficult to efficiently manage complex machine learning tasks across multiple coprocessors.
Innovation Solution
Utilizing global flags asynchronously connected via wires among coprocessors to synchronize tasks, allowing each coprocessor to assert and de-assert flags independently, with a central processing unit managing flag status through control registers and interrupt registers to enforce data and processing dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software interrupts are used for coprocessor synchronization, then coprocessors can be synchronized, but hardware complexity and latency increase
Solution Approach 1:
The patent replaces the software interrupt mechanism with a direct hardware signaling mechanism using shared memory flags. Instead of using complex software interrupt handling and context switching, the system uses simple hardware-level flag setting and clearing operations that can be directly observed and acted upon by coprocessors, thereby reducing both hardware and software complexity while maintaining synchronization reliability
Solution Approach 2:
The patent extracts the synchronization function from the general-purpose software interrupt system and implements it as a dedicated hardware mechanism. By separating the synchronization functionality into a specialized flag-based system with direct coprocessor access, the complexity of the overall system is reduced while synchronization reliability is maintained through dedicated hardware support
2Reliability
If software interrupts are used for coprocessor synchronization, then coprocessors can be synchronized, but processing latency increases
Solution Approach 1:
The patent substitutes the multi-stage software interrupt process with a direct hardware flag mechanism. Coprocessors can immediately detect flag changes through shared memory access without waiting for interrupt context switches, significantly reducing synchronization latency while maintaining reliability through hardware-enforced flag visibility
Solution Approach 2:
The patent implements preliminary action by having the control CPU set synchronization flags in advance before coprocessors need to synchronize. This allows coprocessors to be pre-notified of upcoming synchronization events and prepare accordingly, reducing actual synchronization latency while maintaining reliable coordination
3Productivity
If global flags are used asynchronously, then synchronization speed improves, but hardware complexity increases
Solution Approach 1:
The patent implements universality by using a shared memory structure that serves multiple functions: it stores computation results, maintains synchronization flags, and provides communication between the control CPU and coprocessors. This multi-functional approach enables fast asynchronous synchronization while avoiding the need for separate dedicated hardware structures, thereby limiting the increase in hardware complexity
Data Source
AI summary
Systems and methods for enhanced global flags for synchronizing coprocessors. An example processor system includes a plurality of coprocessors configured to compute a processing task, wherein individual coprocessors are connected to individual remaining coprocessors via a plurality of connections, wherein each connection from a coprocessor to a different coprocessor is configured to be asserted, or de-asserted, to indicate a status associated with a global flag of a plurality of global flags, and wherein the global flag is set based on the plurality of coprocessors asserting the global flag.