Asynchronous Completion Handshaking for Circuit Emulation
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Solution Overview
Problem
Conventional circuit emulators and hardware-assisted logic simulators face issues with catastrophic errors due to clocking system setup and hold violations, leading to reduced design debug efficiency, masked delay faults, and bottlenecks in logic fabrication, requiring operation below intended capacity and throughput.
Innovation Solution
The Hammer Architecture employs a system with asynchronous and synchronous elements at hierarchy borders, using a compiler to embed asynchronous completion handshaking logic into design files, allowing for mixed asynchronous and synchronous operations across chips, boards, and chassis, and enabling independent clocking within units based on data availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clocking systems are used in circuit emulators, then timing analysis and clock distribution can be applied, but setup and hold violations occur causing catastrophic errors
Solution Approach 1:
The patent extracts the clocking system from the emulation architecture entirely, replacing synchronous clocked operation with asynchronous event-driven execution. This eliminates setup and hold violations by removing the clocking mechanism that causes them, while maintaining emulation accuracy through proper handshaking protocols between emulation units.
Solution Approach 2:
Instead of using a clock signal to drive state changes, the patent inverts the control mechanism by using data availability and completion signals to trigger next operations. This asynchronous approach reverses the conventional synchronous paradigm, eliminating timing violations while preserving functional accuracy.
2Reliability
If hardware accelerators are operated below intended capacity to ensure accuracy, then setup and hold violations are avoided, but throughput and performance are reduced
Solution Approach 1:
The patent implements dynamic operation where each emulation unit operates independently at its own optimal speed based on data availability rather than a global clock. This allows the system to achieve both high accuracy and maximum throughput by eliminating the need to operate below capacity, as each unit naturally executes at its intended performance level without timing violations.
Solution Approach 2:
The system performs preliminary preparation of data and control signals before they are needed by downstream units, using asynchronous handshaking to ensure readiness. This allows each unit to operate at full capacity without waiting for clock cycles, maintaining both accuracy and maximum throughput.
3Adaptability or versatility
If manual insertion of emulation elements is required, then design control is maintained, but design complexity and development time increase
Solution Approach 1:
The patent implements self-service by enabling the compilation process to automatically insert the necessary asynchronous handshaking logic and control mechanisms into the emulation design. This eliminates the need for manual insertion of emulation elements, reducing design complexity while maintaining full control over the emulation behavior through the compilation process.
Solution Approach 2:
The compilation process performs preliminary insertion of all necessary asynchronous control logic and handshaking mechanisms before the design is implemented. This automated preliminary action eliminates manual intervention requirements, reducing both design complexity and development time while preserving design adaptability.
4Quantity of substance
If physical hierarchy of hardware accelerators is used, then large logic capacity is achieved, but bottlenecks increase and operation below capacity is required
Solution Approach 1:
The patent segments the hardware accelerator into multiple independent emulation units that operate asynchronously in parallel. This segmentation allows each unit to process data independently at full capacity without creating bottlenecks, as there are no centralized clock distribution or synchronization points that would limit overall throughput. The system achieves both large logic capacity and maximum throughput through this distributed architecture.
Solution Approach 2:
By making each emulation unit dynamically independent with its own timing and control, the system eliminates the bottlenecks inherent in centralized hierarchical architectures. Each unit operates at its intended capacity simultaneously, achieving both large aggregate logic capacity and maximum throughput without requiring operation below capacity.
Data Source
AI summary
An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.