Asynchronous IC Simulation via Ideal Power Node
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Solution Overview
Problem
Current simulation methods for integrated circuits with power management circuitry, such as fast-SPICE and HSIM, are inefficient due to the need for synchronous evaluation of large matrices, leading to sub-optimal performance when simulating large SoC circuits with non-ideal power supplying modules.
Innovation Solution
Designating the output node of a power supply module as an ideal power node allows for asynchronous evaluation of fan-out blocks, enabling parallel and flexible simulation by calculating sensitivity models for each block and loading results into a Jacobian matrix, thereby optimizing system resources and reducing simulation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If synchronous evaluation of large matrices is used in fast-SPICE simulators, then simulation accuracy is maintained, but simulation time increases significantly
Solution Approach 1:
The circuit is partitioned into multiple blocks at the boundary of ideal voltage source nodes and weak coupling nodes. Each block can be evaluated independently or in parallel, reducing the computational burden of synchronous matrix evaluation while maintaining simulation accuracy through proper block decomposition
Solution Approach 2:
The simulator dynamically adjusts the evaluation strategy by identifying which blocks can be evaluated asynchronously based on their coupling relationships. Blocks with independent evaluation opportunities are processed out of strict sequence, optimizing simulation speed without sacrificing accuracy
2Reliability
If the output node of power supply module is treated as non-ideal voltage source, then realistic power network simulation is achieved, but all connected blocks must be evaluated synchronously
Solution Approach 1:
An ideal voltage source node is introduced as an intermediary between the non-ideal power supply output and the connected circuit blocks. This intermediary allows blocks to be decoupled and evaluated independently while still maintaining the realistic non-ideal characteristics of the power supply through appropriate modeling
3Device complexity
If hierarchical partitioning into CCBs is implemented, then circuit complexity is reduced, but flattened partitions still require synchronous evaluation
Solution Approach 1:
The hierarchical partitioning into channel-connected blocks is extended with an additional level of segmentation that identifies independent evaluation opportunities within and across blocks. This multi-level segmentation enables asynchronous evaluation while maintaining the benefits of hierarchical organization
Solution Approach 2:
The evaluation order is made dynamic by continuously identifying blocks that are ready for evaluation based on their dependency relationships. Rather than following a fixed hierarchical order, the simulator adaptively selects which blocks to evaluate next, enabling parallel and asynchronous processing
Data Source
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Figure 1B
Figure 2A~3
AI summary
In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.