Common Asynchronous Interrupt Slots for Time-Synchronous Networks
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Solution Overview
Problem
Existing wireless communication protocols in synchronous control networks, such as IEEE 802.15.4 and CCC standards, fail to meet the fault-tolerant interval requirements for timely communication of critical sensor data, particularly in automotive and industrial systems, leading to increased latency and reduced scalability.
Innovation Solution
Reconfiguring the inter-packet time in a synchronous MAC framework to include a common asynchronous interrupt time slot, allowing secondary devices to transmit interrupt data during this time, reducing latency to a single packet time slot and enabling faster fault detection and response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If existing wireless communication protocols (IEEE 802.15.4, CCC standards) are used in synchronous control networks, then device compatibility and ease of operation are maintained, but latency increases and fault-tolerant interval requirements are not met
Solution Approach 1:
The patent segments the inter-packet time into two distinct portions: a first portion for processing packets received during packet time slots, and a second portion (common asynchronous interrupt time slot) for receiving interrupt information from any secondary device. This segmentation allows interrupt data to be transmitted independently from regular packet communication, reducing latency and ensuring fault-tolerant interval compliance without affecting existing protocol compatibility.
2Adaptability or versatility
If a larger number of secondary devices are added to the network, then network functionality and adaptability increase, but scalability is reduced due to increased complexity in managing packet time slots
Solution Approach 1:
The common asynchronous interrupt time slot serves multiple functions: it allows any secondary device in the network to transmit interrupt information to the primary device regardless of which packet time slot is currently active. This universal interrupt transmission mechanism eliminates the need for individual interrupt handling for each secondary device, enabling support for a larger number of devices without proportionally increasing management complexity.
3Loss of time
If interrupt data transmission is integrated into packet time slots, then device complexity is reduced, but latency for critical fault detection increases
Solution Approach 1:
The patent extracts interrupt information transmission from the packet time slot structure and creates a separate common asynchronous interrupt time slot within the inter-packet time. This extraction allows critical interrupt data to be transmitted independently and immediately upon detection, minimizing fault detection latency. The MAC framework complexity increase is localized to only this interrupt handling mechanism, while regular packet communication remains unaffected.
Data Source
AI summary
Systems, methods, and circuitries are provided for handling non-synchronous interrupts in a time-synchronous network. In one example, a method for a primary device includes monitoring a communication channel during a series of configured packet time slots. Respective packet time slots in the series are mapped to respective secondary devices and successive packet time slots in the series are separated in time from one another by respective inter-packet time. The inter-packet times do not overlap any packet time slot. The method includes monitoring the communication channel during at least one common asynchronous interrupt time slot that occurs during a respective inter-packet time, and generating one or more control signals based on signals received during the packet time slots and the at least one common asynchronous interrupt time slot.