Asynchronous I/O Store Instruction Handling in Data Processing Systems

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Solution Overview

Problem

Current data processing systems face inefficiencies in handling input/output store instructions, particularly in asynchronous execution and error handling, which can lead to delayed operations and increased cycles per instruction when communicating with external devices.

Innovation Solution

A data processing system with an asynchronous core-nest interface and retry logic is introduced, allowing for early completion of input/output store instructions and efficient error detection and retry mechanisms, enabling asynchronous execution before data is stored in external devices and handling errors independently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If synchronous execution is used to ensure data is stored before instruction completion, then reliability is improved, but productivity deteriorates due to increased cycles per instruction

Engineering Contradiction:
Improvedata storage completionVSAvoidcycles per instruction
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary action by allowing the store instruction to be marked as complete before the actual data storage operation finishes. The system prepares completion status indicators in advance and uses them to signal instruction completion to the processor pipeline, enabling the next instruction to proceed without waiting for the actual I/O operation to finish. This decouples instruction completion timing from actual data storage timing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism in the form of a store status register or completion indicator that mediates between the actual data storage operation and the instruction completion signal. This intermediary allows the processor to receive completion notification without directly blocking on the slow I/O operation, effectively acting as a buffer between the fast processor and slow external device.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If asynchronous execution is used to improve productivity, then cycles per instruction is reduced, but reliability deteriorates because data storage completion cannot be guaranteed

Engineering Contradiction:
Improvecycles per instructionVSAvoiddata storage completion
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms through status registers that track the completion state of asynchronous store operations. The system continuously monitors whether data has been successfully stored and provides feedback signals to indicate completion status. This allows the processor to proceed asynchronously while still having reliable information about when storage actually completes, enabling proper error handling and retry logic if needed.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent prepares completion status indicators and tracking mechanisms in advance of the actual data storage operation. By setting up the asynchronous completion tracking infrastructure beforehand, the system can immediately begin the store operation without waiting, while still maintaining the ability to reliably detect when storage completes through pre-configured status registers and completion flags.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If error handling is performed synchronously to ensure reliability, then error detection accuracy is improved, but productivity deteriorates due to operation delays

Engineering Contradiction:
Improveerror detection accuracyVSAvoidoperation speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements preliminary error handling by setting up error detection mechanisms and retry logic in advance of actual store operations. Error checking code and retry counters are prepared beforehand, allowing the system to quickly handle errors asynchronously without blocking the main instruction stream. This enables rapid error detection and automated retry attempts without sacrificing operational throughput.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary error status registers and exception handling mechanisms that mediate between asynchronous store operations and synchronous error processing. These intermediaries capture error conditions during asynchronous operations and buffer them for later processing, allowing the main instruction stream to continue without interruption while errors are handled through separate exception processing paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If multiple store operations are outstanding simultaneously to improve productivity, then throughput is increased, but device complexity increases due to tracking requirements

Engineering Contradiction:
Improvestore operation throughputVSAvoidtracking mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the tracking of multiple store operations into separate, independently manageable status indicators. Each outstanding store operation is assigned its own completion flag or status register entry, allowing the system to track multiple operations simultaneously without complex interdependencies. This segmentation simplifies the tracking mechanism by breaking down the monolithic tracking problem into discrete, manageable units that can be handled independently.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11593107B2Handling an input/output store instruction
Publication Date: 2023.02.28 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11593107B2 patent drawing
  • US11593107B2 patent drawing
  • US11593107B2 patent drawing

AI summary

An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.