Asynchronous Reconfigurable Logic Fabric Without Clock Synchronization

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Solution Overview

Problem

Conventional reconfigurable logic fabrics are limited by sequential synchronous circuits, which restrict their operational speed and compatibility with existing electronic design automation tools.

Innovation Solution

The development of asynchronous reconfigurable logic fabrics that operate independently of clock signals, utilizing dataflow operations represented as 'tokens' and implemented with asynchronous logic blocks, memory blocks, and interconnect elements to enable faster and more flexible logical operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If sequential synchronous circuits are used in reconfigurable logic fabric, then compatibility with existing EDA tools is maintained, but operational speed is limited due to clock cycle waiting delays

Engineering Contradiction:

Improveoperational speedVSAvoidcompatibility with EDA tools

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The logic fabric is segmented into independent logic blocks that can operate asynchronously without requiring global clock synchronization. Each logic block functions as an autonomous unit, enabling faster local operations while maintaining interface compatibility with EDA tools through standardized configuration protocols.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of using synchronous circuits that wait for clock cycles, the invention inverts the approach by using asynchronous circuits where logic blocks operate independently and signal completion through handshaking mechanisms. This reversal eliminates the fundamental speed limitation of sequential waiting while preserving EDA tool compatibility through abstraction layers.

Inventive Principle:

Principle #13The other way round (Inversion)

2Speed

If asynchronous logic blocks are used to increase operational speed, then computational speed increases to 1GHz levels, but circuit design complexity increases

Engineering Contradiction:

Improvecomputational speedVSAvoidcircuit design complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The logic blocks are designed as universal asynchronous units that can perform multiple logic functions through reconfigurable interconnections. This multi-functionality reduces the number of different circuit types needed, simplifying the overall design process while maintaining high-speed asynchronous operation across the entire fabric.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Standardized interface circuits act as intermediaries between the asynchronous logic blocks and the configuration system. These intermediary elements handle the complexity of asynchronous handshaking and synchronization, shielding designers from the intricacies of asynchronous design while enabling 1GHz operational speeds in the core logic blocks.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7880499B2Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics

Publication Date: 2011.02.01 ACHRONIX SEMICONDUCTOR CORP

AI summary

In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics (302, 304) for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.