Asynchronous Reconfigurable Logic Fabric Without Clock Cycle Delays
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Solution Overview
Problem
Conventional reconfigurable logic fabrics are limited by sequential arrangements of synchronous circuits, which restrict their operational speed and compatibility with existing electronic design automation tools.
Innovation Solution
The development of asynchronous reconfigurable logic fabrics that operate independently of clock signals, utilizing dataflow operations represented by 'tokens' and implemented in programmable logic blocks, memory blocks, and multiplier blocks, allowing for faster and more flexible logical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If synchronous circuits are arranged sequentially in reconfigurable logic fabric, then the fabric can be configured using conventional EDA tools, but the operational speed is limited due to clock cycle delays between circuits
Solution Approach 1:
The patent inverts the conventional synchronous approach by implementing asynchronous logic elements that do not rely on clock signals. Instead of having circuits wait for clock cycles, the asynchronous elements operate independently and propagate signals immediately when computation is complete, thereby eliminating the clock cycle delay bottleneck while maintaining configurability through adapted EDA tool flows
2Reliability
If clock signals are used to synchronize circuit operations, then circuit timing can be controlled, but computational speed is limited by the clock frequency
Solution Approach 1:
The patent replaces periodic clock signals with event-driven asynchronous operation. Logic elements operate periodically only when data is available, rather than waiting for periodic clock edges. This allows computational speed to be determined by actual data arrival and computation completion times rather than fixed clock frequency, thereby increasing productivity while maintaining timing reliability through handshaking protocols
Solution Approach 2:
The patent changes the fundamental timing parameter from fixed clock frequency to variable event-driven timing. Each asynchronous logic element can operate at different speeds based on its specific computation requirements, allowing the overall system to achieve higher effective computational speed without sacrificing timing control, as each element's timing is adapted to its specific needs rather than constrained by a global clock
Data Source
AI summary
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.