Asynchronous Logic Fabric With Synchronous I/O Compatibility
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Solution Overview
Problem
Conventional reconfigurable logic fabrics are limited by synchronous circuits, which restrict their operational speed and compatibility with existing electronic design automation (EDA) tools.
Innovation Solution
An integrated circuit with a reconfigurable logic fabric comprising asynchronous logic elements, including a multiplier unit and memory unit, coupled with a programmable input/output block for synchronous operation with external circuits, enabling faster and more efficient logic operations without relying on a global clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous circuits are used in reconfigurable logic fabric, then compatibility with EDA tools is maintained, but operational speed is limited due to clock cycle delays
Solution Approach 1:
The logic fabric is segmented into multiple asynchronous logic elements that can operate independently without a global clock. Each logic element processes signals autonomously, eliminating the need to wait for clock cycle synchronization. This segmentation allows parallel operation of multiple logic elements, significantly increasing operational speed while maintaining design flexibility.
Solution Approach 2:
Instead of using synchronous circuits that wait for clock signals, the patent inverts the approach by using asynchronous circuits where signals propagate immediately when ready. The handshaking mechanism inverts the traditional clock-driven paradigm, allowing logic operations to complete as soon as data is available rather than waiting for the next clock edge, thereby resolving the speed limitation.
2Speed
If asynchronous logic elements are used to increase speed, then operational speed improves, but compatibility with synchronous external circuits and EDA tools deteriorates
Solution Approach 1:
Synchronous interface circuits are introduced as intermediaries between the asynchronous logic fabric and synchronous external circuits. These interface circuits translate between asynchronous handshaking signals and synchronous clocked signals, allowing the high-speed asynchronous core to communicate with standard synchronous external circuits without sacrificing speed advantages or compatibility.
Solution Approach 2:
The patent applies different operational modes to different parts of the system: asynchronous operation within the logic fabric for high speed, and synchronous operation at the interfaces for compatibility. This local differentiation allows each part to operate in its optimal mode, maintaining both high computational speed and ease of operation with external circuits.
3Productivity
If sequential arrangements of synchronous circuits are used, then design using EDA tools is simplified, but speed is limited by clock cycle waiting delays
Solution Approach 1:
The global clock signal is extracted and removed from the logic fabric, eliminating the source of synchronization delays. Logic elements operate autonomously using local handshaking signals instead of waiting for global clock cycles. This extraction of the clock mechanism removes the fundamental limitation on computational throughput while reducing the complexity of clock distribution and synchronization.
4Speed
If logic elements wait for clock cycles to receive computation results, then synchronous operation is maintained, but operational speed decreases
Solution Approach 1:
A handshaking feedback mechanism is implemented where logic elements signal each other when computation is complete and when data is ready. This feedback replaces the blind waiting for clock cycles with active notification, allowing immediate data transfer when ready while maintaining reliable operation through explicit acknowledgment signals between logic elements.
Data Source
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AI summary
In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics (302, 304) for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics.