Asynchronous Memory Element for Overlapping Set Reset Signals
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Solution Overview
Problem
Existing memory elements, such as flip-flops and latches, face challenges in high-frequency applications due to overlapping set and reset signals, leading to metastable states and incorrect logical outputs, which are not adequately addressed by current solutions.
Innovation Solution
A memory element comprising a persistence latch network and an asynchronous circuit that retains a logical state between the edges of the set and reset signals, ensuring the output remains stable regardless of input signal overlap, using persistence latches to provide persistent outputs and an asynchronous logic circuit to control the timing window for input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional flip-flops or latches are used for high-frequency operation, then the switching speed is improved, but overlapping set and reset signals cause metastable states and incorrect logical outputs
Solution Approach 1:
The memory element is divided into two independent bistable circuits, each handling one input signal (set or reset). This segmentation allows each circuit to independently process its input without interference, preventing metastable states that occur in traditional single-circuit flip-flops when inputs overlap. Each bistable circuit maintains its own stable state, ensuring reliable logical outputs even during high-frequency operation with overlapping signals.
2Reliability
If additional gates are added to convert the 1-1 state to non-restricted combinations, then the logical correctness is improved, but the device complexity increases
Solution Approach 1:
The problematic 1-1 state conversion logic is extracted and eliminated by using two separate bistable circuits instead of one circuit with additional conversion gates. Each bistable circuit independently handles set or reset signals, so the forbidden 1-1 state never occurs. This extraction of the problematic state handling mechanism simplifies the overall circuit design while maintaining logical correctness.
Solution Approach 2:
The two bistable circuits act as intermediaries that process set and reset signals separately before producing the final output. Instead of using complex gating logic to handle input conflicts, the intermediary bistable circuits naturally resolve conflicts through their independent stable states, reducing the need for additional control gates and simplifying the circuit.
3Reliability
If clocked flip-flops are used to ensure correct operation, then the logical stability is improved, but the power consumption and electromagnetic interference increase
Solution Approach 1:
The memory element uses asynchronous bistable circuits that are self-triggering and do not require external clock signals. Each bistable circuit automatically responds to its input signal (set or reset) and maintains its state without needing periodic clocking. This self-service operation eliminates the continuous power consumption and electromagnetic interference associated with clocked flip-flops while maintaining logical stability through the inherent stability of the bistable circuits.
Data Source
AI summary
A memory element is provided in which a logical state can be securely stored in all conditions even when input set and reset signals are overlapping. This is achieved through provision of an array of persistence latches with an asynchronous circuit that ensures correct operation. The persistence latches provide a persistent output for each of the first and second edges of each input. The memory element is arranged to receive a plurality of inputs including a first and second input. Each first and second inputs include a digital signal that can transition between a first state via a first edge which triggers transition from the first state to the second state and a second edge which triggers transition from the second state to the first state.