Asynchronous On-Die Termination Control for Memory I/O Pins
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Solution Overview
Problem
Conventional on-die termination (ODT) circuits require external clock synchronization and additional pins for enabling termination resistors, leading to increased power consumption and complexity in memory devices.
Innovation Solution
An ODT circuit that selectively provides different termination impedances based on logic levels of DOEN and ACS signals, using a switching control unit and termination resistor unit to adjust impedance asynchronously with respect to a clock signal, eliminating the need for an ODT enable signal and reducing the number of external pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ODT circuits use external clock synchronization and ODT enable pins, then the termination circuit can be controlled, but power consumption increases and device complexity increases
Solution Approach 1:
The patent extracts the clock synchronization function and ODT enable pin from the conventional ODT circuit. The termination circuit is controlled directly by the DOEN signal without requiring external clock synchronization, thereby eliminating the need for additional synchronization circuitry and reducing power consumption while maintaining reliable ODT control.
Solution Approach 2:
The patent merges the ODT control function with the existing DOEN signal generation circuitry. The termination circuit uses the same clock signal that drives the output buffer enable logic, eliminating the need for separate clock synchronization circuits and reducing overall device complexity and power consumption.
2Reliability
If conventional ODT circuits use external clock synchronization, then the termination circuit can be controlled, but the number of external pins increases
Solution Approach 1:
The patent removes the ODT enable pin from the external interface. The termination circuit is controlled internally by the DOEN signal that is already generated based on the output buffer enable logic, eliminating the need for additional external pins and reducing device complexity.
Solution Approach 2:
The DOEN signal serves multiple functions: it enables the output buffer and simultaneously controls the termination circuit. This multi-functional approach eliminates the need for separate ODT enable pins, reducing the number of external pins required while maintaining reliable control.
3Adaptability or versatility
If conventional ODT circuits provide fixed termination impedance, then the circuit is simple, but it cannot provide optimal termination for different memory modes (READ, WRITE, NORMAL)
Solution Approach 1:
The patent implements a dynamic termination circuit that automatically adjusts the termination impedance based on the memory operation mode. The termination resistor is selectively connected or disconnected in response to the DOEN signal state, providing different termination impedances for READ, WRITE, and NORMAL modes without requiring complex manual control.
Solution Approach 2:
The patent changes the termination impedance parameter dynamically based on the operational mode. By controlling the connection state of the termination resistor through the DOEN signal, the circuit provides optimal termination impedance (e.g., 50 ohms for READ, 120 ohms for WRITE) for each mode, improving adaptability while keeping the circuit relatively simple.
Data Source
AI summary
An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command. The memory device may further comprise a training circuit comprising: an asynchronous signal delay configured to delay the signal path of the ACS signal to the termination circuit; and a comparing unit configured to compare a phase difference between the ACS signal and a reference signal, the comparing unit comprising a phase detector and a replica delay, wherein the replica delay is configured to delay the signal path of the ACS signal to the phase detector, and the phase detector is configured to output the phase difference as training result.