Asynchronous Pipeline Circuit With Variable Request Signal Delay
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Solution Overview
Problem
Asynchronous pipelines face inefficiencies due to fixed request signal delays, leading to idle stages waiting for the delay to expire, which increases overall pipeline processing time, as the actual processing time varies based on data bit state changes.
Innovation Solution
Incorporating a variable delay line into the request signal path with a tap encoder that adjusts the delay based on state changes in specific data bits, allowing the request signal to be transmitted closer to the actual processing time required by each stage, thereby minimizing idle time and reducing overall processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed request signal delay equal to or greater than the maximum possible processing time is used, then the request signal timing requirement is met, but pipeline stages sit idle waiting for the delay to expire, increasing overall processing time
Solution Approach 1:
The patent applies dynamics by replacing the fixed request signal delay with a variable delay mechanism. The delay is dynamically adjusted based on the actual processing time of the logic block, allowing the system to adapt to different data processing scenarios. This resolves the contradiction by making the delay flexible rather than static, ensuring timing requirements are met while minimizing idle time.
Solution Approach 2:
The patent changes the parameter of request signal delay from a fixed value to a variable value that depends on the actual processing time. By monitoring the processing time of the logic block and adjusting the delay accordingly, the system maintains reliable timing while reducing the excessive delay that causes idle stages, thus resolving the technical contradiction.
2Stability of the object's composition
If a fixed request signal delay is used to ensure proper handshaking, then data stability is guaranteed, but the pipeline processing speed decreases due to stages waiting for the delay to expire
Solution Approach 1:
The patent makes the request signal delay dynamic rather than fixed. The delay adjusts based on the actual processing time of each logic block, ensuring data stability is maintained while allowing the pipeline to operate at higher speeds by eliminating excessive waiting time in idle stages.
Solution Approach 2:
The patent implements feedback by monitoring the processing time of the logic block and using this information to adjust the request signal delay. This feedback mechanism ensures that the delay is optimized for each specific processing scenario, maintaining data stability while maximizing pipeline processing speed.
3Productivity
If the request signal is sent early to reduce idle time, then processing speed improves, but the request signal may arrive before data is stable, causing errors
Solution Approach 1:
The patent changes the request signal delay from a fixed conservative value to a variable value that is precisely tuned to the actual processing time. This allows the request signal to be sent at the optimal time - early enough to maintain high processing speed but late enough to ensure data stability, thus resolving the contradiction.
Solution Approach 2:
The patent uses preliminary monitoring of the logic block processing time to determine the appropriate delay before sending the request signal. This preliminary action ensures that the request signal is timed correctly based on actual processing requirements, preventing both premature arrival and excessive waiting.
Data Source
AI summary
Disclosed are embodiments of an asynchronous pipeline circuit. In each stage of the circuit, a variable delay line is incorporated into the request signal path. A tap encoder monitors data entering the stage to detect any state changes occurring in specific data bits. Based on the results of this monitoring (i.e., based on which of the specific data bits, if any, exhibit state changes), the tap encoder enables a specific tap in the variable delay line and, thereby, automatically adjusts the delay of a request signal transmitted along the request signal path. Using a variable request signal delay allows data from a transmitting stage to be captured by a receiving stage prior to the expiration of the maximum possible processing time associated with the transmitting stage, thereby minimizing overall processing time. Also disclosed are embodiments of methods for asynchronous pipeline processing with variable request signal delay and for incorporating variable request signal delay into an asynchronous pipeline circuit design.