Asynchronous Power-Down Control in Semiconductor Memory Devices
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Solution Overview
Problem
Semiconductor devices face increased current consumption and potential malfunctions due to the need for an internal clock signal to be constantly toggled during power-down mode transitions, leading to abnormal signal generation when switching between high-speed and low-speed operations.
Innovation Solution
A semiconductor memory device that asynchronously controls the entry/exit operation into/from power-down mode by delaying and sequencing control signals independently of the internal clock signal, using a timing controller to deactivate and activate these signals in specific sequences to prevent signal abnormalities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal clock signal is toggled at all times to synchronize the clock enable signal, then abnormal glitches are prevented, but current consumption increases
Solution Approach 1:
The patent extracts the clock enable signal processing from the synchronous clock domain and creates an independent asynchronous processing path. The timing controller generates control signals (first to third control signals) that are independent of the internal clock signal, eliminating the need for continuous clock toggling while maintaining signal stability during power-down mode transitions.
Solution Approach 2:
The patent introduces a timing controller as an intermediary that generates intermediate control signals to manage the power-down mode transitions. These control signals mediate between the external clock enable signal and the internal circuitry, ensuring proper sequencing without requiring synchronous clock alignment.
2Adaptability or versatility
If the clock buffer is changed during power-down mode to adapt to frequency changes, then operational flexibility is improved, but signal abnormalities occur due to improper buffering
Solution Approach 1:
The patent applies preliminary action by controlling the clock buffer before the power-down mode transition occurs. The timing controller generates control signals that prepare the clock buffer in advance, ensuring it is properly configured before the frequency change happens, thus preventing signal abnormalities during the transition.
Solution Approach 2:
The patent implements dynamic control of the clock buffer by adjusting its operation based on the power-down mode state. The clock buffer's behavior changes dynamically according to the control signals generated by the timing controller, allowing it to adapt to different operational modes while maintaining signal integrity.
Data Source
AI summary
According to an embodiment of the present disclosure, a semiconductor memory device includes a first buffer circuit suitable for receiving a command/address signal to output a first buffered signal according to a first control signal; a first setup/hold circuit suitable for delaying the first buffered signal to output an internal command/address signal according to a second control signal; a command decoder suitable for generating a plurality of internal signals by decoding the internal command/address signal according to a third control signal and an internal dock signal; and a timing controller suitable for delaying a dock enable signal to generate the first to third control signals, and controlling the first to third control signals to be deactivated in a first sequence when entering a power-down mode, and to be activated in a second sequence different from is the first sequence when exiting the power-down mode.