Asynchronous Control Queue With Symmetric Forward and Reverse Latency

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Solution Overview

Problem

Existing asynchronous circuits face challenges in synchronizing component actions due to increasing clock speeds, and there is a need for control queues with equal item flow and bubble flow latencies, which is difficult to achieve with existing designs.

Innovation Solution

A control queue is designed with modules that have equal forward and reverse latencies, constructed using GasP modules, where the present module asynchronously generates outputs based on inputs and alternates polarity, and successive modules alternate between 2-4 and 4-2 GasP configurations, ensuring equal latency for both signal directions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional control queue designs are used, then either forward or reverse latency is reduced, but the other latency increases creating asymmetry

Engineering Contradiction:
Improvecontrol signal latencyVSAvoidlatency balance
Core Design Contradiction:
Loss of timeVSEase of operation

Solution Approach 1:

The patent applies asymmetry in reverse - it deliberately designs symmetric latency by using complementary asymmetric modules. The 4-2 GasP module (4 delays forward, 2 delays reverse) is paired with the 2-4 GasP module (2 delays forward, 4 delays reverse) in alternating sequence. This creates overall symmetry where total forward latency equals total reverse latency, resolving the contradiction between reducing one latency direction and maintaining operational balance.

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The control queue is segmented into multiple control modules, each implementing decision-wait functionality. By dividing the queue into discrete modules with specific latency characteristics (4-2 and 2-4 GasP modules), the system can balance overall latency through strategic module selection and arrangement, rather than treating the queue as a monolithic structure.

Inventive Principle:
Principle #1Segmentation

2Speed

If 4-2 GasP modules are used, then forward latency increases to four delays, but reverse latency decreases to two delays

Engineering Contradiction:
Improvereverse signal speedVSAvoidforward signal delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent uses the 2-4 GasP module as a counterweight to the 4-2 GasP module. The 2-4 module has reversed latency characteristics (2 delays forward, 4 delays reverse) that compensate for the asymmetry introduced by the 4-2 module. When arranged in alternating sequence, these modules counterbalance each other's latency asymmetry, achieving overall symmetric latency performance.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

3Productivity

If control queues operate half-full, then balanced latency is most beneficial, but existing designs cannot provide equal forward and reverse latencies

Engineering Contradiction:
Improvesystem performanceVSAvoidlatency equality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the latency parameters of the control queue by selecting and arranging specific GasP module types (4-2 and 2-4) in alternating sequence. This parameter configuration ensures that the sum of forward delays equals the sum of reverse delays across the entire queue, achieving precise latency equality optimized for half-full queue operation conditions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7436861B2Asynchronous control circuit with symmetric forward and reverse latencies
Publication Date: 2008.10.14 ORACLE AMERICAN INC
  • US7436861B2 patent drawing
  • US7436861B2 patent drawing
  • US7436861B2 patent drawing

AI summary

One embodiment of the present invention provides a control queue for an asynchronous circuit that includes a number of control modules coupled together linearly to form the control queue. These control modules include a prior module, a present module, and a next module. The present module is configured to receive one or more forward-going inputs from the prior module and one or more reverse-going inputs from the next module. The present module asynchronously generates one or more forward-going outputs to the next module and one or more reverse-going outputs to the prior module. The modules within the control queue are constructed so that the latency of the forward-going signals through the control queue is equal to the latency of the reverse-going signals through the control queue.