Asynchronous Sampling Rate Conversion Using Buffer Tracking and PLL
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Solution Overview
Problem
Existing sampling rate converters require additional synchronization hardware or complex timing protocols, leading to increased cost, complexity, and processing overhead, especially when dealing with mismatched sampling rates between transmitting and receiving devices.
Innovation Solution
A software-based asynchronous sampling rate converter (ASRC) that tracks buffer read and write operations to determine a rate control value, using a polyphase interpolator and a phase-locked loop to adjust for temperature variations and noise, eliminating the need for separate synchronization hardware and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sampling rate converters are used, then sampling rate conversion can be achieved, but additional synchronization hardware and complex timing protocols are required, increasing device complexity and cost
Solution Approach 1:
The patent replaces traditional hardware-based synchronization mechanisms with a software-based approach. The ASRC uses a polyphase interpolator and counter mechanism implemented in software to achieve sampling rate conversion, eliminating the need for additional synchronization hardware and timing protocols while maintaining conversion accuracy
Solution Approach 2:
The ASRC system is self-synchronizing through its internal counter mechanism that automatically adjusts to sampling rate variations. The counter increments on input samples and decrements on output samples, automatically adapting to rate changes without requiring external synchronization signals or additional hardware
2Reliability
If traditional sampling rate converters are used, then sampling rate conversion can be achieved, but processing overhead increases due to complex timing protocols
Solution Approach 1:
The patent replaces complex timing protocols with a simple counter-based software mechanism. The counter increments for each input sample and decrements for each output sample, providing a computationally efficient method that reduces processing overhead while maintaining accurate sampling rate conversion
Solution Approach 2:
The patent uses a polyphase interpolator that creates interpolated output samples based on input samples. This software-based interpolation approach efficiently generates the required output samples without requiring complex timing operations, reducing processing overhead
3Reliability
If buffer size is increased to handle sampling rate variations, then buffer overflow/underflow is prevented, but memory usage and system resources increase
Solution Approach 1:
The patent implements a dynamic buffer management approach where the buffer size and operations are adapted based on the current sampling rate conditions. The counter mechanism dynamically tracks the buffer state, allowing the system to handle sampling rate variations with a moderate buffer size by adjusting operations in real-time rather than requiring a excessively large fixed buffer
Data Source
AI summary
Aspects of the disclosure relate to asynchronous sampling rate conversion of digital audio data. A sampling rate conversion module may use, for sampling rate conversion, a bank of subfilters corresponding to a polyphase interpolator. The specific subfilters and/or filter coefficients to be used for generation of output samples may be based on a rate control value. The rate control value may be determined based on tracking a number of read operations and a number of write operations associated with a buffer storing the output samples. A phase-locked loop (PLL) or other control loop may be used to maintain the rate control value at an appropriate level to negate the effects of temperature variations and noise on sampling rates.