Asynchronous Device Rescheduling via Dedicated Time Slots
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Solution Overview
Problem
Asynchronous devices operating independently of a global clock system exhibit processing cycle divergence due to manufacturing tolerances, leading to issues like master/slave dependency, device failure, and 'babbling idiot' events, which existing synchronization mechanisms fail to address effectively.
Innovation Solution
A rescheduling mechanism that adjusts the processing cycles of asynchronous devices without relying on a master/slave principle, using dedicated processing time slots for rescheduling signals, ensuring fault tolerance and low cost implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a master/slave synchronization mechanism is used to prevent divergence between asynchronous devices, then system stability is improved, but device complexity and vulnerability to single points of failure increase
Solution Approach 1:
The patent divides the processing cycle into distinct segments: a major frame for primary processing and a dedicated processing slot for rescheduling operations. This segmentation allows each device to maintain its own independent timing while periodically synchronizing, eliminating the need for continuous master/slave dependency and reducing vulnerability to single points of failure.
Solution Approach 2:
The patent implements periodic rescheduling signals exchanged between devices at predetermined intervals during dedicated processing slots. This periodic synchronization maintains system stability without requiring continuous master/slave relationships, allowing devices to operate independently between synchronization events and reducing complexity.
2Measurement precision
If continuous synchronization signals are exchanged to maintain alignment between devices, then processing cycle alignment is improved, but system robustness to failures deteriorates
Solution Approach 1:
The patent incorporates predetermined wait states and timeout mechanisms that allow the system to handle missed synchronization signals gracefully. These cushioning elements absorb the impact of communication failures or device malfunctions, preventing single points of failure from causing system-wide divergence while maintaining alignment during normal operation.
3Stability of the object's composition
If processing cycles are continuously adjusted to maintain synchronization, then divergence is prevented, but processing efficiency decreases
Solution Approach 1:
The patent segments the processing cycle into a major frame for primary processing tasks and a separate dedicated processing slot for rescheduling operations. This allows the majority of processing time to be devoted to productive work while limiting synchronization overhead to specific, bounded intervals, thereby maintaining processing cycle consistency without continuously impeding processing efficiency.
Data Source
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AI summary
An asynchronous first device (1) in communication with an asynchronous second device (11) is described herein; wherein the time for the first device (1) to complete a processing cycle is a first device major frame (3); wherein the first device major frame (3) comprises a first device dedicated processing time slot (5) at the end of the first device major frame (3), wherein the first device (1) is configured to send a rescheduling signal to the second device (11) when it has completed a first device major frame (3); and wherein the first device (1) is configured, during every first device dedicated processing slot (5), to: monitor for a rescheduling signal sent from the second device (11) to the first device (1); and if a rescheduling signal from the second device (11) is received: reschedule the current first device major frame (3) to a rescheduled first device major frame (3'); wherein the end of the rescheduled first device major frame (3') coincides with the time the rescheduling signal from the second device (11) was received, and wherein each subsequent rescheduled first device major frame (3') starts as soon as the previous rescheduled first device major frame (3') has ended.