Asynchronous Routing Network for Programmable Circuit Blocks
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Solution Overview
Problem
As integrated circuits evolve with increasing voltage and frequency domains, conventional circuits face challenges in transferring signals quickly due to limitations in metal conductors and require complex timing control, leading to issues like increased capacitance, delay, and significant clock loading, especially in devices with programmable resources that need synchronous communication.
Innovation Solution
A programmable integrated circuit with a routing network enabling asynchronous data communication between circuit blocks, using configurable routing circuits that function as shift registers for clockless time multiplexing and convert single-ended data to dual rail data for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous communication with global clock networks is used, then timing control is enabled, but area overhead and clock skew issues increase
Solution Approach 1:
The patent extracts and removes the global clock network from the system by implementing asynchronous communication between circuit blocks. Each block operates independently without requiring a global clock distribution network, thereby eliminating the area overhead associated with clock routing while maintaining reliable timing control through handshaking protocols and local synchronization mechanisms.
Solution Approach 2:
The patent segments the circuit into independent blocks that communicate asynchronously rather than relying on a unified synchronous clock network. This segmentation allows each block to operate autonomously with its own local timing, eliminating the need for extensive global clock distribution infrastructure and reducing area overhead while preserving timing control through block-level coordination.
2Ease of manufacture
If metal conductors are used for signal transfer, then circuit implementation is simplified, but signal transfer speed becomes insufficient for fast transistors
Solution Approach 1:
The patent implements dynamic voltage scaling and frequency domain separation, allowing different circuit blocks to operate at optimized voltages and frequencies. This dynamic approach enables faster signal transfer in critical paths by using higher voltage domains where necessary, while maintaining ease of manufacture through standardized cell libraries and modular design that accommodate multiple voltage domains without requiring entirely new manufacturing processes.
3Speed
If wider and taller conductors are implemented to increase speed, then signal transfer speed improves, but capacitance and delay increase
Solution Approach 1:
The patent applies local quality optimization by implementing voltage scaling and conductor sizing specific to each circuit block's performance requirements. Rather than uniformly increasing conductor dimensions across the entire chip, the patent uses larger conductors only in critical high-speed paths where needed, while using smaller, lower-capacitance conductors in non-critical paths. This localized approach maintains signal transfer speed where required while minimizing overall capacitance and energy loss.
4Productivity
If pipelining with flip flops is used to increase throughput, then data throughput improves, but clock loading increases significantly
Solution Approach 1:
The patent extracts the global clock dependency from the pipelining structure by implementing asynchronous communication between pipeline stages. Instead of using heavily loaded global clock signals to synchronize flip-flops across the entire chip, the patent allows each pipeline stage to operate independently with local handshaking signals, thereby maintaining high data throughput while eliminating the clock loading problem associated with synchronous pipelining.
Data Source
AI summary
A programmable integrated circuit is disclosed. The programmable integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising configurable blocks; and a routing network coupled to each circuit block of the plurality of circuit blocks, the routing network enabling asynchronous data communication with the plurality of circuit blocks. Each circuit block comprises an interface portion having routing circuits coupled to the routing network, the routing circuits enabling routing data to the configurable blocks of the circuit block. A method of asynchronously routing data in a circuit block of an integrated circuit is also disclosed.