Asynchronous Sample Rate Conversion for Jitter-Stable Audio Clocks
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Solution Overview
Problem
Existing signal processing systems face challenges in efficiently converting input signals with arbitrary sample rates to synchronized output signals, particularly in mobile and consumer electronic devices, which can lead to glitches due to asynchronous sample rates, requiring efficient and cost-effective sample rate converters that can handle multiple output sample rates with minimal additional hardware.
Innovation Solution
A signal processor with an asynchronous sample rate converter, comprising a cross enable unit, a finite impulse response (FIR) filter module, and a linear interpolation unit, which generates resampled clock signals and de-jittered signals to produce a stabilized output sample rate, capable of handling multiple input signals and converting them into multiple resampled output signals with variable sample rates without significant hardware additions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sample rate conversion methods are used to convert arbitrary input sample rates to synchronized output sample rates, then signal synchronization is achieved, but hardware complexity and cost increase significantly
Solution Approach 1:
The ASRC core is designed to handle multiple input signals with different sample rates and convert them to multiple output signals with different target sample rates using the same hardware structure, eliminating the need for dedicated conversion circuits for each signal pair
Solution Approach 2:
The system dynamically adjusts the resampling ratio parameter based on the input and desired output sample rates, allowing flexible conversion between arbitrary sample rates without requiring hardware reconfiguration
2Adaptability or versatility
If multiple sample rate converters are implemented to handle different output sample rates, then versatility is improved, but hardware resources and cost increase
Solution Approach 1:
A single ASRC core performs multiple sample rate conversions by changing the resampling ratio parameter, supporting any combination of input and output sample rates without requiring additional conversion circuits
Solution Approach 2:
The resampling ratio is made dynamically adjustable based on the desired output sample rate, allowing the same hardware to adapt to different conversion requirements in real-time
3Stability of the object's composition
If synchronous sampling is used to maintain signal integrity, then signal stability is improved, but the system cannot handle asynchronous input clocks without glitches
Solution Approach 1:
The ASRC acts as an intermediary between asynchronous input clocks and the synchronous system clock, absorbing clock variations and converting them to a stable output rate without causing glitches in the signal processing chain
Solution Approach 2:
The system preemptively handles clock rate variations by using the ASRC to compensate for asynchronous sampling before the signals enter the synchronous processing pipeline, preventing synchronization issues from propagating
Data Source
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AI summary
An asynchronous sample rate converter and method for converting an input signal to a resampled output signal is disclosed. An efficient and cost-effective sample rate converter for converting an input signal of arbitrary sample rate to a resampled output signal of a second sample rate is disclosed. A hardware-efficient sample-rate converter for resampling an audio input signal with an arbitrary sample rate to an output audio signal with a known sample rate for use in an audio processor is disclosed.