Asynchronous Sampling Rate Conversion with Polyphase PLL Control
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Solution Overview
Problem
Mismatched sampling rates between transmitting and receiving devices in digital signal processing can lead to signal distortion and buffer overflow/underflow, necessitating additional synchronization hardware that increases cost and complexity.
Innovation Solution
Employing a software-based asynchronous sampling rate converter (ASRC) that uses time stamps and local clocks to determine packet write and read rates, coupled with a polyphase interpolator and phase-locked loop to adjust sampling rates, eliminating the need for separate synchronization hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional synchronization hardware is used to match sampling rates between transmitting and receiving devices, then signal distortion and buffer overflow/underflow are prevented, but device complexity and cost increase
Solution Approach 1:
The patent replaces physical synchronization hardware with a software-based asynchronous sampling rate converter (ASRC) that uses digital signal processing algorithms. The ASRC determines packet write rates from time stamps, calculates rate control values, and dynamically adjusts sampling rates through software control, eliminating the need for additional hardware components while maintaining signal synchronization reliability
Solution Approach 2:
The patent dynamically changes the sampling rate parameter based on the calculated rate control value. The ASRC adjusts the number of output data samples generated from input samples according to the ratio between packet write rate and packet read rate, allowing flexible adaptation to different sampling rate requirements without hardware modification
2Adaptability or versatility
If a software-based ASRC is used to convert sampling rates dynamically, then device complexity is reduced and flexibility is improved, but measurement precision of sampling rate conversion may be affected by temperature variations and noise
Solution Approach 1:
The patent implements a phase-locked loop (PLL) or control loop that continuously monitors the sampling rate conversion process and adjusts the rate control value to maintain accuracy. The feedback mechanism compensates for temperature variations and noise by dynamically correcting the sampling rate conversion, ensuring measurement precision is maintained despite environmental factors
Solution Approach 2:
The patent uses time stamps associated with input data packets to determine the packet write rate before conversion occurs. By calculating the rate control value in advance based on these time stamps and the packet read rate, the system prepares the correct conversion parameters beforehand, ensuring accurate sampling rate conversion even under varying conditions
Data Source
AI summary
Aspects of the disclosure relate to asynchronous sampling rate conversion of digital data. A sampling rate conversion module may use, for sampling rate conversion, a bank of subfilters corresponding to a polyphase interpolator. The specific subfilters and/or filter coefficients to be used for generation of output samples may be based on a rate control value. The rate control value may be determined based on a sampling rate used for input samples of the sampling rate converter and a read-out rate associated with samples, generated by the sampling rate converter, stored in an output buffer. A phase-locked loop (PLL) or other control loop may be used to maintain the rate control value at an appropriate level to negate the effects of temperature variations, noise, or any other system variations on the sampling rates.