Asynchronous Sampling Rate Converter for Digital Radio Clock Synchronization
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Solution Overview
Problem
Digital radio receivers face challenges in adjusting their audio sampling rate without synchronizing the receiver clock with the transmitter clock, leading to potential buffer overflow or underflow and subsequent audio distortions, especially in systems where the receiver baseband processor is not the master of the receiver clock.
Innovation Solution
A method and system that determine the phase difference between the receiver and transmitter clocks to adjust the sampling rate by generating frames with varying numbers of samples, using an asynchronous sampling rate converter to synchronize the receiver sampling rate with the transmitter rate, allowing for dynamic adjustment of sample output based on the phase difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the receiver baseband processor is not the master of the receiver clock, then the system architecture is more flexible, but the sampling rate cannot be adjusted without causing buffer overflow or underflow
Solution Approach 1:
An asynchronous sampling rate converter is introduced as an intermediary component between the decoder and the audio processing pipeline. This converter acts as a mediator that handles the sampling rate conversion without requiring the baseband processor to be the clock master, thus maintaining architectural flexibility while ensuring buffer stability through controlled sample generation.
Solution Approach 2:
The invention changes the sampling rate parameter dynamically by adjusting the number of samples generated in each frame based on the phase difference between receiver and transmitter clocks. This allows the system to adapt to different clock conditions without changing the fundamental architecture or requiring the baseband processor to control the clock.
2Device complexity
If the sampling rate is adjusted without clock synchronization, then the system complexity is reduced, but audio distortions occur due to buffer overflow or underflow
Solution Approach 1:
The system implements a feedback mechanism by determining the phase difference between the receiver and transmitter clocks and using this information to adjust the number of samples generated in each frame. This feedback loop allows the system to compensate for sampling rate differences without requiring complex clock synchronization, thereby preventing buffer overflow or underflow and avoiding audio distortions.
Solution Approach 2:
The invention introduces dynamic adjustment of the sampling rate by varying the number of samples per frame based on the determined phase difference. This dynamic approach allows the system to adapt to changing clock conditions in real-time without requiring complex synchronization hardware, thus reducing device complexity while preventing audio distortions.
3Reliability
If frames with varying numbers of samples are generated, then the sampling rate is synchronized with the transmitter, but the processing timing becomes more complex
Solution Approach 1:
The invention changes the number of samples parameter in each frame based on the phase difference between clocks, allowing the system to synchronize the sampling rate with the transmitter. This parameter-based approach achieves synchronization through software-controlled sample generation rather than complex hardware timing circuits, thereby maintaining reliability while managing processing timing complexity.
Data Source
AI summary
Methods and systems for adjusting a sampling rate of a digital radio receiver are disclosed that comprise the steps of receiving from a decoder a first frame of data having a first number of samples; determining at the digital radio receiver a phase difference between a receiver clock and a transmitter clock; generating at the digital radio receiver a second frame of data having a second number of samples, wherein the second number of samples depends on the phase difference between the receiver clock and the transmitter clock such that the second number of samples is less than the first number of samples if the transmitter clock is ahead of the receiver clock, and the second number of samples is greater than the first number of samples if the receiver clock is ahead of the transmitter clock; outputting the second frame of data having the second number of samples; and requesting a next frame of data from the decoder at a time that is earlier than a processing time for the first number of samples if the transmitter clock is ahead of the receiver clock and at a time that is later than the processing time for the first number of samples if the receiver clock is ahead of the transmitter clock such that the next frame of data from the decoder and a next transmitter frame are synchronized, and wherein whether the second number of samples is greater than or less than the first number of samples is determined by whether the sampling rate is increased or decreased.