Asynchronous SAR ADC Calibration for Non-Ideal Effect Removal
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Solution Overview
Problem
Asynchronous SAR ADCs cannot self-calibrate, leading to worse product characteristics and lower yield rates due to non-ideal effects, unlike their synchronous counterparts.
Innovation Solution
Integration of a calibration circuit, memory device, and asynchronous control circuit in the digital control circuit of the SAR ADC, allowing for calibration and storage of calibration information to remove non-ideal effects when operating in asynchronous mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous control mode is used for high-speed operation, then speed and power efficiency are improved, but non-ideal effects cause worse product characteristics and lower yield
Solution Approach 1:
The patent applies preliminary action by performing calibration operations before the asynchronous SAR ADC is applied or used. The calibration circuit pre-calibrates the ADC to remove non-ideal effects such as capacitor mismatch and comparator offset, storing calibration data in advance. This ensures that when the ADC operates in asynchronous mode for high-speed conversion, the previously identified non-ideal effects have already been compensated, thereby maintaining both high speed and good product characteristics.
Solution Approach 2:
The patent introduces a calibration circuit as an intermediary component between the input signal and the conversion process. This calibration circuit performs preliminary calibration to identify and compensate for non-ideal effects in the DAC, capacitor array, and comparator. By using this intermediary calibration mechanism, the system can operate in asynchronous mode with high speed while the calibration circuit continuously or periodically removes the harmful non-ideal effects, resolving the contradiction between speed and reliability.
2Reliability
If synchronous control mode is used for self-calibration, then product characteristics are improved, but conversion speed and power efficiency are reduced
Solution Approach 1:
The patent separates the calibration function from the normal conversion operation. The calibration circuit performs self-calibration as a preliminary action before normal operation, or during idle periods, using synchronous control mode only when needed for calibration. Once calibration is complete, the system switches to asynchronous control mode for high-speed conversion. This time-separated approach allows the system to enjoy the benefits of self-calibration without continuously sacrificing conversion speed.
Solution Approach 2:
The patent implements dynamic switching between synchronous and asynchronous control modes. The system dynamically selects the appropriate control mode based on the operational requirement: synchronous mode is used during calibration phases to ensure accuracy, while asynchronous mode is used during normal high-speed conversion operations. This dynamic adaptability allows the system to optimize performance for each specific task, resolving the contradiction between calibration accuracy and conversion speed.
3Device complexity
If calibration circuit is integrated into digital control circuit, then device complexity is reduced, but calibration functionality must be added to existing structure
Solution Approach 1:
The patent merges the calibration circuit with the existing digital control circuit of the SAR ADC. The calibration circuit shares resources such as the DAC, capacitor array, and comparator with the normal conversion function. By integrating the calibration functionality into the existing structure rather than adding completely separate calibration hardware, the overall device complexity is minimized while still achieving comprehensive calibration coverage for all critical components.
Solution Approach 2:
The patent implements multi-functionality by designing the calibration circuit to use the same hardware resources (DAC, capacitor array, comparator) for both normal conversion operations and calibration operations. The digital control circuit dynamically configures these shared resources to perform either calibration or conversion based on the current operational mode. This universal use of components reduces the need for dedicated calibration hardware, simplifying the overall device structure while maintaining comprehensive calibration capability.
Data Source
AI summary
A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.