Asynchronous SAR ADC Redundancy for Faster Stable Conversion
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) face limitations in speed due to the settling time of digital-to-analog converters (DACs) and metastability issues in comparators, leading to inefficiencies in high-resolution conversions.
Innovation Solution
The implementation of asynchronous SAR ADCs with overlapping redundant bits in DAC code words, utilizing a timer to generate a preemptive decision signal when the comparator's decision time exceeds a threshold, ensuring the analog input voltage difference is within an overlapping voltage range, thereby reducing settling time and preventing metastability errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SAR ADC architecture is used, then high resolution is achieved, but conversion speed is limited due to DAC settling time and comparator metastability
Solution Approach 1:
The patent applies preliminary action by initiating the DAC settling process before the comparator decision is made. The system allows the DAC to settle for a predetermined time period, and only after this settling period expires does the comparator attempt to make a decision. This sequencing ensures that the DAC has sufficient time to stabilize, preventing metastability errors while maintaining high conversion speed through asynchronous operation.
Solution Approach 2:
The patent implements dynamics by using an asynchronous SAR ADC architecture where the conversion process is not rigidly synchronized to a clock signal. Instead, each bit conversion step proceeds independently based on the settling time requirements, allowing the system to dynamically adapt to varying signal conditions and optimize both resolution and speed performance.
2Measurement precision
If DAC settling time is increased to improve accuracy, then measurement precision improves, but conversion speed decreases
Solution Approach 1:
The system performs the DAC settling action preliminarily and independently before the comparison operation. By allocating a dedicated settling period that occurs before the comparator decision, the system ensures adequate voltage stabilization without forcing the entire conversion process to wait, thus improving measurement precision while minimizing time loss through parallel/asynchronous operation.
Solution Approach 2:
The conversion process is segmented into distinct phases: DAC settling phase and comparator decision phase. This segmentation allows each phase to be optimized independently - the settling phase ensures voltage accuracy while the decision phase captures the result, preventing the need to extend the total conversion time proportionally to settling requirements.
3Reliability
If comparator decision time is extended to prevent metastability, then reliability improves, but productivity decreases
Solution Approach 1:
The system performs the critical settling action preliminarily before the comparator decision. By ensuring the DAC has already settled to the required accuracy before the comparator begins its evaluation, the comparator can make reliable decisions more quickly without needing to extend its decision time, thus improving both reliability and productivity through proper sequencing.
Solution Approach 2:
The settling period acts as an intermediary between the DAC output and the comparator input. This intermediary phase ensures that the comparator receives a stable, settled voltage signal, reducing metastability events and improving decision reliability without requiring the comparator itself to operate slower or for extended periods.
Data Source
AI summary
An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.