Asynchronous Serial Signal Encoding Without PLL Clock Synchronization
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Solution Overview
Problem
Existing digital signal transmitting apparatuses face issues with erroneous transmission due to clock variations, particularly when they operate asynchronously without a PLL circuit, leading to prolonged startup times and increased circuit size.
Innovation Solution
A digital signal transmitting apparatus that includes an encoder to convert parallel input signals into serial data synchronized with a first clock and a decoder to convert the serial data into parallel output signals using an asynchronous second clock, with counters and discriminators to determine the period and duty factor of the serial data, allowing for error suppression even with clock variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL circuit is used to synchronize clocks, then transmission reliability is improved, but circuit size increases and startup time is prolonged
Solution Approach 1:
The patent extracts and eliminates the PLL circuit from the system by adopting an asynchronous transmission architecture. The encoder and decoder operate with independent clocks without requiring phase-locked synchronization, thereby removing the source of increased circuit size and startup time while maintaining transmission reliability through duty ratio encoding schemes.
Solution Approach 2:
The patent changes the synchronization parameter from phase-based synchronization (requiring PLL) to duty ratio-based encoding. By embedding clock synchronization information within the duty ratio of data signals rather than requiring separate clock synchronization circuits, the system achieves reliable transmission without increasing circuit complexity.
2Reliability
If a PLL circuit is used to synchronize clocks, then transmission reliability is improved, but startup time is prolonged
Solution Approach 1:
The patent removes the PLL circuit that causes startup delay, allowing the system to begin operation immediately without requiring lock time for clock synchronization. The asynchronous architecture with duty ratio encoding enables immediate data transmission upon system initialization.
Solution Approach 2:
The patent embeds clock synchronization information in advance within the duty ratio of transmitted data signals. The receiver can extract timing information from the incoming data stream itself, eliminating the need for preliminary clock synchronization operations and reducing startup time.
3Device complexity
If independent clocks are used in encoder and decoder for asynchronous transmission, then circuit size is reduced, but transmission errors occur due to clock variation
Solution Approach 1:
The patent changes from phase-based clock synchronization to duty ratio-based encoding. By embedding timing and synchronization information within the duty ratio parameter of data signals, the system maintains transmission reliability with independent clocks. The receiver decodes both data and timing information from the same signal, eliminating errors caused by clock variation.
Solution Approach 2:
The patent implements implicit feedback by encoding clock synchronization information within the transmitted data signals themselves. The duty ratio of received signals provides feedback about timing relationships, allowing the receiver to adjust its interpretation of data without requiring separate synchronization signals or increasing circuit complexity.
Data Source
AI summary
A digital signal transmitting apparatus includes an encoder which converts parallel input signals of multiple channels into serial data in a manner synchronized with a first clock signal, and a decoder which converts the serial data into parallel output signals of the multiple channels in a manner synchronized with a second clock signal operating in a manner asynchronous with the first clock signal. The serial data has a different period and a different duty factor corresponding to each combination of the logical values of the parallel input signals of the multiple channels.