Asynchronous Spike Counting Interface Without High-Speed Clocks
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Solution Overview
Problem
The increase in network size in spike neural networks implemented with semiconductor circuits leads to an increase in the number of physical wires and I/O count, causing a design burden and increased power consumption due to the use of high-speed clocks for asynchronous-synchronous timing between the spike neural network and digital domain.
Innovation Solution
An asynchronous spike counting interface apparatus using counters and a memory-structure-based address decoder to count neuron firings, eliminating the need for high-speed clocks by synchronizing counters with delayed request signals and acknowledging asynchronous operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If address encoders and decoders are implemented to deliver spikes using addresses as network size increases, then the number of physical wires and I/O count are reduced, but power consumption increases due to the use of high-speed sampling clocks for asynchronous-synchronous timing
Solution Approach 1:
The patent extracts the high-speed sampling clock from the interface apparatus and relocates it to the digital domain only. The interface apparatus uses asynchronous operation with hand-shaking signals (REQ/ACK) to communicate with the digital domain, eliminating the need for high-speed clocks in the analog spike neural network portion while maintaining address-based spike delivery functionality
Solution Approach 2:
The patent introduces hand-shaking signals (request REQ and acknowledgement ACK) as intermediaries between the asynchronous spike neural network and the synchronous digital domain. These mediator signals enable timing coordination without requiring high-speed sampling clocks, allowing the address decoder to operate asynchronously while still synchronizing with the digital domain when needed
2Reliability
If high-speed sampling clocks are used in the digital domain to recognize asynchronously delivered output spike addresses and REQ signal, then timing between asynchronous spike neural network and digital domain is achieved, but design burden and power consumption increase
Solution Approach 1:
The patent implements dynamic timing coordination where the interface apparatus adapts its operation mode based on communication needs. The address decoder can operate in fully asynchronous mode using hand-shaking signals, or coordinate with the digital domain clock when address recognition is required, providing flexible timing management without fixed high-speed clock requirements
Solution Approach 2:
The patent uses acknowledgement (ACK) signals as feedback mechanisms from the digital domain to the interface apparatus. This feedback loop allows the asynchronous spike neural network to know when the digital domain has successfully received and processed address information, enabling reliable asynchronous-synchronous timing coordination without high-speed sampling clocks
Data Source
AI summary
Disclosed herein are an asynchronous spike counting interface apparatus and an asynchronous spike counting method in a spike neural network. The asynchronous spike counting interface apparatus may include multiple counters, each counting the number of times each of neurons included in the spike neural network fires, and an address decoder for outputting an enable signal to the counter that counts the number of times the neuron corresponding to the address output from the spike neural network fires.