At-Memory Hash Architecture Without Shift Registers or Clock Trees
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Solution Overview
Problem
Distributed ledger technologies, such as cryptocurrency mining, face high levels of power consumption due to hash operations, particularly in devices with limited power reserves like mobile handsets and laptops, necessitating a more energy-efficient hashing solution.
Innovation Solution
Implementing at-memory computing (AMC) architectures for hashing systems that reduce power consumption by minimizing data movement and rotation between storage elements, using combinational logic and memory cells like RAM or SRAM, and eliminating the need for clock trees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional hashing techniques using shift registers and clock trees are used, then hash computation can be performed, but power consumption is high
Solution Approach 1:
The patent extracts and removes the clock tree infrastructure from the hashing system, eliminating the need for clock signals to synchronize shift registers. This extraction of the timing mechanism enables asynchronous operation, directly reducing power consumption while maintaining hash computation capability through alternative timing methods at the logic gate level.
Solution Approach 2:
The patent replaces the mechanical/clock-based synchronization system (clock trees and clock signals) with a logic-level timing mechanism where timing is inherent to the logic gate operations themselves. This substitution eliminates the need for high-frequency clock distribution while maintaining computational functionality.
2Use of energy by moving object
If data is physically moved between registers using shift registers, then hash computation is enabled, but power consumption increases
Solution Approach 1:
The patent uses copying by creating multiple instances of logic gates that operate in parallel to process different bits simultaneously. Instead of physically moving data through shift registers, the data is copied and processed by duplicate logic units, eliminating the need for sequential data movement while maintaining computational throughput.
Solution Approach 2:
The patent segments the hash computation into independent bit-level operations that can be performed simultaneously by separate logic gate instances. This segmentation allows parallel processing without requiring data to be physically shifted between registers, as each bit position is handled by its own dedicated logic unit.
3Device complexity
If clock trees are used to synchronize register operations, then hash computation can proceed, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes the clock tree infrastructure from the hashing system, eliminating the need for clock signals to synchronize shift registers. This extraction of the timing mechanism enables asynchronous operation, directly reducing power consumption while maintaining hash computation capability through alternative timing methods at the logic gate level.
Solution Approach 2:
The logic gates inherently self-time their operations based on signal propagation delays and logic level transitions, eliminating the need for external clock synchronization. Each logic gate automatically times its operation based on when input signals arrive and when the gate completes its logical function, providing self-service timing without clock trees.
Data Source
AI summary
A hashing system includes data storage circuit elements that store words to be used for hashing a message. Each data storage circuit element stores a word without moving the word to any other data storage circuit element during hashing. The hashing system includes combinational logic circuit element(s) that select specified data storage circuit elements according to a specified order that simulates shifting of at least a subset of the words among the data storage circuit elements, for instance based on an order in which the words were stored and/or based a clock. The hashing system includes computational operator(s) that generate additional word(s) based on the selected specified words. The hashing system stores the additional word(s) into available data storage circuit element(s), in some cases overwriting prior word(s) that were stored in the available data storage circuit element(s). The hashing system can include a message expander (ME) and/or message compressor (MC).