At-Speed Memory BIST Failure Bitmap Locking
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Solution Overview
Problem
Conventional semiconductor device testing methods face challenges in detecting memory failures at high speeds due to bandwidth limitations, which can lead to undetected faults and reduced fault coverage, especially in large memories operating at frequencies above 1 GHz.
Innovation Solution
The implementation of a built-in self-test circuitry with failure capturing logic that captures and stores failure data in device internal registers, allowing for the creation of a bitmap that can be read out at any time, enabling detection of speed-critical memory failures without bandwidth restrictions, using a pipeline architecture to process and store failure results efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory testing is performed at high speeds above 1 GHz, then testing speed and productivity are improved, but bandwidth limitations cause loss of information and reduced fault coverage
Solution Approach 1:
The patent segments the memory testing process into multiple pipeline stages, where each stage processes a portion of the test data independently. This allows high-speed testing to proceed through multiple parallel processing paths, capturing failure data at different stages without bandwidth bottlenecks limiting overall fault coverage.
Solution Approach 2:
The patent introduces a temporal dimension by storing failure data in synchronized registers across pipeline stages, allowing data to be captured and held for later retrieval. This transforms the bandwidth limitation from a spatial constraint into a time-managed resource, preserving all failure information regardless of testing speed.
2Measurement precision
If failure data is captured and stored in device internal registers, then fault coverage and measurement precision are improved, but device complexity increases
Solution Approach 1:
The patent makes existing pipeline registers serve dual functions: their primary function in data processing and an additional function for storing failure data. By synchronizing these registers to capture failure information, the patent avoids adding dedicated storage elements, thereby improving fault detection accuracy while minimizing increases in device complexity.
Solution Approach 2:
The failure capturing mechanism utilizes the existing infrastructure of the memory interface and pipeline stages to store and retrieve failure data. The system serves its own testing needs by repurposing existing resources rather than requiring separate dedicated test equipment, thereby reducing overall device complexity while maintaining high measurement precision.
3Productivity
If bandwidth is increased to support high-speed testing, then productivity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements periodic capture of failure data at synchronized intervals throughout the pipeline, rather than requiring continuous high-bandwidth data transfer. This allows the memory interface to operate at reduced bandwidth during normal operation while maintaining high testing throughput through efficient periodic sampling of failure conditions.
Solution Approach 2:
The patent creates simplified copies of failure data in register form that can be read out independently from the main memory interface. Instead of requiring the full memory bandwidth to carry all test data, the system creates compact failure result copies that can be extracted through lower-bandwidth channels, thereby maintaining high productivity without increasing interface complexity.
Data Source
AI summary
In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.