At-Speed Structural Test Pattern Generation for IC Timing Paths
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Solution Overview
Problem
Current integrated circuit (IC) testing methods face challenges in achieving broad test coverage of the process space efficiently, as the number of timing paths increases with integration scale, leading to impractical and costly approaches that fail to accurately measure test coverage and detect small delay defects caused by process variations.
Innovation Solution
A method involving statistical timing analysis and criticality analysis to determine criticality probabilities for nodes and timing paths, followed by generating at-speed structural test patterns to selectively test critical paths, thereby improving test coverage and reducing testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all timing paths are tested for all possible combinations of timing-influencing parameters, then test coverage of process space is improved, but testing time and complexity become impractical
Solution Approach 1:
The patent segments the complete set of timing paths into critical and non-critical paths based on statistical timing analysis. By identifying only the critical paths that are most likely to be affected by process variations, the testing scope is reduced from all paths to a subset, making testing feasible while maintaining adequate coverage of the process space.
Solution Approach 2:
The patent uses statistical timing analysis to change the approach from deterministic timing analysis to probabilistic timing analysis. This parameter change allows the system to evaluate timing paths based on their criticality probability rather than fixed timing constraints, enabling selective testing of paths with highest criticality scores.
2Device complexity
If static timing analysis is used to identify critical paths, then testing complexity is reduced, but false paths and poor process coverage result
Solution Approach 1:
The patent replaces deterministic static timing analysis with statistical timing analysis. This substitution uses probabilistic models to evaluate timing paths, replacing the mechanical/deterministic approach with a statistical one that better captures process variations and identifies truly critical paths without generating false positives.
Solution Approach 2:
The patent incorporates feedback from statistical timing analysis results into the test selection process. By using criticality probabilities calculated from statistical timing data, the system iteratively refines which paths to test, improving both the accuracy of process coverage measurement and the efficiency of testing.
3Productivity
If at-speed structural testing is performed without considering critical paths, then testing speed is improved, but functional validation and detection of small delay defects are compromised
Solution Approach 1:
The patent applies local quality by differentiating treatment for different timing paths. Rather than uniformly testing all paths at full speed, the system identifies critical paths that require special attention and applies at-speed structural testing selectively to these paths, ensuring reliable defect detection where it matters most while maintaining overall testing efficiency.
Data Source
AI summary
A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.