At-Speed IC Test Power Control via PEP Segmentation
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Solution Overview
Problem
Existing methods for reducing power consumption during at-speed testing of integrated circuits are coarse-grained and fail to address local power density and dynamic IR drop issues effectively, leading to hotspots and inefficiencies in power grid management.
Innovation Solution
The creation of power equivalent polygons (PEPs) to overlay power density information and clock gate locations, followed by grouping and generating unique test control signals for each clock gate to minimize simultaneous activation and reduce IR drop hotspots, using a virtual constraint function to selectively enable test control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If coarse-grained power reduction techniques are used during at-speed testing, then overall power consumption is reduced, but local power density and dynamic IR drop issues are not effectively addressed
Solution Approach 1:
The patent segments the chip into multiple power domains by creating power equivalent polygons (PEPs) that group clock gates into distinct regions. Each power domain can be independently controlled with its own test control signal, enabling localized power management rather than global coarse-grained control. This segmentation allows precise control of local power density while maintaining overall power reduction.
Solution Approach 2:
The patent implements local quality by assigning different test control signals to different power domains based on their specific power density characteristics and IR drop risks. Each power domain receives customized control signals that address its local power management needs, rather than applying uniform coarse-grained control across the entire chip. This enables targeted reduction of local IR drop hotspots.
2Reliability
If multiple test control signals are generated for different clock gates, then local IR drop hotspots are reduced, but test control complexity increases
Solution Approach 1:
The patent merges the control of multiple clock gates by grouping them into power domains based on spatial proximity and power density characteristics represented by overlapping PEPs. Clock gates within the same power domain share a common test control signal, reducing the total number of control signals needed while still providing fine-grained local control. This merging approach balances IR drop reduction effectiveness with control complexity.
Solution Approach 2:
The patent introduces a spatial dimension to power control by using power equivalent polygons to represent the physical layout and power density distribution of clock gates. This geometric representation adds a spatial organizing principle that simplifies the management of multiple test control signals by grouping clock gates based on their physical locations and power characteristics rather than treating them as isolated individual controls.
3Reliability
If clock gates are activated simultaneously during testing, then test coverage is improved, but power consumption and thermal issues increase
Solution Approach 1:
The patent implements periodic action by enabling test control signals in a staggered or phased manner across different power domains rather than simultaneously activating all clock gates. Test patterns are applied sequentially or in waves across power domains, maintaining adequate test coverage while distributing power consumption over time. This temporal distribution prevents peak power spikes and thermal hotspots.
Data Source
AI summary
Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.