At-Speed Transition Delay Fault Test Optimization
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Solution Overview
Problem
Current semiconductor testing methods are inefficient in determining effective voltage and temperature test conditions for at-speed transition delay fault tests, leading to increased testing costs and defect detection challenges.
Innovation Solution
A method involving a test analyzer that analyzes scan patterns, identifies activated paths, determines worst-case test corners, generates histograms, and selects thresholds based on quality metrics to create an ordered test set for testing semiconductor devices, optimizing test conditions and reducing the number of test corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semiconductor testing methods are used to determine test conditions for at-speed transition delay fault tests, then comprehensive fault coverage can be achieved, but testing time and costs increase significantly
Solution Approach 1:
The patent performs preliminary analysis of scan patterns and identification of activated paths before actual testing. By determining worst-case test corners and generating histograms in advance, the system prepares optimized test conditions beforehand, avoiding the need for extensive trial-and-error testing and reducing overall testing time while maintaining fault coverage
Solution Approach 2:
The patent extracts and focuses only on the most critical test conditions by identifying activated paths and determining worst-case test corners. By taking out and prioritizing only the essential test scenarios that provide maximum fault coverage, the system eliminates unnecessary testing at less critical conditions, thereby reducing testing time and costs
2Reliability
If multiple test corners are used to ensure comprehensive defect detection, then defect detection capability improves, but testing costs increase
Solution Approach 1:
The patent changes the parameters of test conditions by determining worst-case test corners and generating histograms that show the distribution of paths at different corners. By selectively applying test conditions based on these parameter optimizations, the system achieves effective defect detection at critical corners while avoiding redundant testing at non-critical corners, thus reducing testing costs
Solution Approach 2:
The patent applies partial action by focusing testing efforts on the most critical test corners that provide the highest defect detection value. Rather than uniformly testing all possible corners, the system identifies and concentrates resources on the subset of corners that are most likely to reveal defects, achieving cost-effective testing
3Reliability
If comprehensive test conditions are applied to all scan patterns, then fault detection coverage is maximized, but testing efficiency decreases
Solution Approach 1:
The patent segments the testing process into distinct phases: analyzing scan patterns, identifying activated paths, determining worst-case test corners, generating histograms, and selecting thresholds. This segmentation allows the system to process and optimize test conditions in manageable steps, improving efficiency while maintaining comprehensive fault detection coverage
Solution Approach 2:
The patent incorporates feedback mechanisms by using histogram analysis and quality metrics to evaluate test conditions. The system uses this feedback to iteratively optimize the selection of test corners and scan patterns, ensuring that testing efficiency is continuously improved while maintaining fault detection coverage
Data Source
AI summary
An example method for determining test conditions for at-speed transition delay fault tests on semiconductor devices is provided and includes analyzing scan patterns for testing a circuit of a device-under-test (DUT), identifying paths in the circuit activated by the scan patterns, determining behavior of the paths at different test corners, generating a histogram for each scan pattern representing a distribution of paths exhibiting worst-case behavior at corresponding test corners, generating an ordered set of scan pattern-test corner combinations based on the histogram, selecting a threshold for the ordered scan pattern-test corner combinations based on quality metrics, generating an ordered test set including the ordered scan pattern-test corner combinations with the selected threshold, and feeding the ordered test set to a test instrument, the test instrument testing the DUT according to the ordered test set, the tests being performed at the test corners listed above the selected threshold.