Address Translation Cache Lookup Using Redundancy Bits
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Solution Overview
Problem
Existing address translation cache (ATC) solutions in data storage devices are inefficient, leading to high cost, power consumption, and performance issues due to the need for large SRAM caches and complex lookup operations.
Innovation Solution
Implementing a redundancy bit system in data storage devices, where redundancy bits are calculated and compared to a table to quickly identify matches in the ATC, allowing early retrieval of translated addresses, with most of the ATC stored in DRAM and redundancy bits in flops, reducing the need for SRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a real cache for ATC is implemented as defined in the PCIe standard, then address translation functionality is supported, but device area, cost and power consumption significantly increase
Solution Approach 1:
The patent extracts only the essential functionality needed for address translation by implementing a simplified ATC that caches only translation results rather than implementing a full PCIe-standard cache. This extraction approach maintains the core address translation capability while removing unnecessary cache structures that would consume device area, cost, and power.
Solution Approach 2:
The patent employs a lightweight ATC implementation that uses minimal cache resources compared to the PCIe standard. Instead of maintaining a large, persistent cache structure, the system uses a simplified cache that is updated on-demand and uses significantly less hardware resources, thereby reducing area, cost, and power consumption while maintaining functional reliability.
2Reliability
If a real cache for ATC is implemented as defined in the PCIe standard, then address translation functionality is supported, but power consumption significantly increases
Solution Approach 1:
The patent extracts only the essential functionality needed for address translation by implementing a simplified ATC that caches only translation results rather than implementing a full PCIe-standard cache. This extraction approach maintains the core address translation capability while removing unnecessary cache structures that would consume power.
Solution Approach 2:
The patent employs a lightweight ATC implementation that uses minimal cache resources compared to the PCIe standard. Instead of maintaining a large, persistent cache structure, the system uses a simplified cache that is updated on-demand and uses significantly less hardware resources, thereby reducing area, cost, and power consumption while maintaining functional reliability.
3Adaptability or versatility
If ATC is implemented with large memory cache buffer, then address translation capability is improved, but device cost increases
Solution Approach 1:
The patent extracts only the essential functionality needed for address translation by implementing a simplified ATC that caches only translation results rather than implementing a full PCIe-standard cache. This extraction approach maintains the core address translation capability while removing unnecessary cache structures that would increase device cost.
Solution Approach 2:
The patent employs a lightweight ATC implementation that uses minimal cache resources compared to the PCIe standard. Instead of maintaining a large, persistent cache structure, the system uses a simplified cache that is updated on-demand and uses significantly less hardware resources, thereby reducing area, cost, and power consumption while maintaining functional reliability.
Data Source
AI summary
Redundancy bits can be used to more effectively manage address translation cache (ATC) in data storage devices. The data storage device maintains a table of redundancy bits. When a request for an address translation arrives, the redundancy bits are calculated and compared to redundancy bits in the table. If there is a match, then the relevant ATC entry is retrieved and compared to the untranslated addresses. The same process is repeated for each redundancy bits match until finding a match in the ATC. In so doing, the translated address can be requested much earlier than normal by requesting the translated address upon the redundancy bits not matching. The earlier retrieval reduces throughput of the memory device without reducing performance. Furthermore, the unique structure of the internal ATC allows most of the ATC to be located in SRAM/DRAM while simply the redundancy bits are stored in flops.