Address Transition Detection Circuit Area Reduction
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Solution Overview
Problem
Existing address transition detection circuits require a minimum delay unit for each address line, leading to a large area requirement on integrated circuits, which is inefficient in terms of layout space.
Innovation Solution
A signal transition detection circuit that uses a comparator and storage element for each address signal line, with a wired-OR network to generate an ATD signal, eliminating the need for separate minimum delay units and allowing for a more compact layout by combining comparison results across multiple address lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a minimum delay unit is used for each address line in the prior art, then address transition detection can be achieved, but the area required on the integrated circuit becomes large
Solution Approach 1:
The patent merges the delay functionality into a shared delay unit that is common to all address lines, rather than having separate delay units for each address line. This consolidation reduces the total area while maintaining the ability to detect address transitions across multiple lines simultaneously.
Solution Approach 2:
The delay unit is designed to serve multiple address lines universally, performing the delay function for any address line that requires it. This multi-functional approach eliminates the need for dedicated delay units for each address line, thereby reducing overall circuit area.
2Measurement precision
If separate minimum delay units are provided for each address line, then accurate transition detection is achieved, but the circuit complexity and layout area increase
Solution Approach 1:
Multiple address line processing is merged into a single delay unit structure, reducing circuit complexity while preserving detection accuracy through proper signal routing and comparison logic.
Solution Approach 2:
The circuit is segmented into functional blocks (delay unit, comparison unit, output logic) that can be independently optimized, allowing accurate transition detection without requiring complex interconnections between multiple delay units.
Data Source
AI summary
A new address transition detection (ATD) circuit for use on an address bus having a plurality of address signal lines comprises a first circuit for each address signal line and a second circuit. The first circuit has a first input, a second input and an output. The first input is coupled to an address signal line. The second input is coupled to an ATD signal. The first circuit saves the current level of the first input in response to an ATD pulse on the ATD signal and generates a change signal at its output by comparing the current level and the saved level of the first input. The second circuit has an input and an output. The second circuit receives on its input the change signal from the first circuit. In response, the second circuit generates the ATD pulse on the ATD signal at its output.