ATE FPGA Frequency Doubling via Accelerator and Decelerator
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Solution Overview
Problem
Conventional automatic test equipment (ATE) for semiconductor devices is limited by the maximum operating frequency of its field programmable gate array (FPGA), which restricts the capability to test high-speed semiconductor memory devices like DDR2 or DDR3 DRAM, as the FPGA's frequency cannot exceed 400 MHz due to capacitance issues.
Innovation Solution
Incorporating an accelerator and a decelerator into the ATE system, connected to the FPGA, which doubles the operating frequency to 800 MHz and converts it back to 400 MHz, respectively, allowing for higher-speed testing without requiring new hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the FPGA operates at its maximum frequency limited by capacitance (400 MHz), then the system is stable and reliable, but the testing speed of high-speed semiconductor memory devices cannot be achieved
Solution Approach 1:
The patent segments the signal processing function into three independent parts: the FPGA operates at its stable maximum frequency (400 MHz) for control and coordination, while separate accelerator circuits handle high-speed signal generation and decelerator circuits handle high-speed signal reception. This segmentation allows each component to operate at its optimal frequency without compromising system stability.
Solution Approach 2:
The patent introduces accelerator and decelerator circuits as intermediary components between the FPGA and the high-speed semiconductor memory device. These intermediaries bridge the frequency gap by converting the FPGA's 400 MHz signals to higher frequencies for testing, while the FPGA itself remains stable at 400 MHz.
2Productivity
If the FPGA frequency is increased beyond 400 MHz to test high-speed devices, then testing capability improves, but capacitance issues cause system instability
Solution Approach 1:
The patent divides the testing system into a stable FPGA core operating at 400 MHz and separate high-speed accelerator/decelerator circuits. This segmentation allows the FPGA to maintain stability while the peripheral circuits handle high-speed testing, thereby improving productivity without sacrificing reliability.
Solution Approach 2:
The patent uses accelerator and decelerator circuits as functional copies that handle the high-frequency signal processing tasks. Instead of increasing the FPGA frequency, these copying circuits replicate the signal processing function at higher frequencies, enabling high-speed testing while the original FPGA remains stable.
3Speed
If conventional ATE hardware is used with FPGA limited to 400 MHz, then hardware complexity is low, but high-speed semiconductor memory device testing cannot be performed
Solution Approach 1:
The patent makes the accelerator and decelerator circuits universal components that can work with the existing FPGA architecture. These circuits are designed to interface with the standard FPGA output/input terminals, allowing the system to achieve high-speed testing capabilities without requiring a complete hardware redesign, thus balancing speed improvement with acceptable complexity.
Data Source
AI summary
Automatic test equipment is capable of performing a high-speed test of semiconductor devices, with a low cost and high efficiency. The automatic test equipment (ATE) comprises: an ATE body configured to electrically test semiconductor devices; a field programmable gate array (FPGA) controlling drivers and comparators on the ATE; an accelerator connected to an output terminal of the FPGA and that doubles an operating frequency of the FPGA; and a decelerator connected to an output terminal of the FPGA and that converts an operating frequency of data transferred from the semiconductor device to the operating frequency of the FPGA.