ATE Path Selection for Memory Interface Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current at-speed testing methods for memory circuits, such as ATPG and BIST, fail to effectively test the true data path through the functional interface of memory, especially in complex architectures with memory self-loops and increased logic depth, leading to incomplete fault detection and potential test escapes.
Innovation Solution
A test override circuit that selectively controls data access between multiple memory instances and logic endpoints using a path selector and gating circuit, responding to test control signals from ATE, enabling dynamic construction of testing paths and mitigating test escapes by allowing individual control of data, clock, and output paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If ATPG or BIST methods are used for memory testing, then automated testing capability is provided, but the true data path through the functional interface is not tested
Solution Approach 1:
The patent implements dynamic path selection by enabling the memory interface to switch between functional mode and test mode. In test mode, the path selector dynamically routes test patterns through the true data path from functional logic through the memory interface, allowing automated testing while actually exercising the critical paths that ATPG and BIST previously missed.
Solution Approach 2:
The patent introduces a test override circuit as an intermediary component that sits between the memory interface and the external tester. This circuit includes a path selector and gating circuits that mediate the flow of test patterns, enabling external control of the data paths while maintaining the existing memory interface architecture.
2Adaptability or versatility
If complex memory architectures with self-loops and arbitration logic are used, then memory functionality is enhanced, but ATPG controllability and observability deteriorate
Solution Approach 1:
The patent segments the memory interface testing into distinct controllable paths using gating circuits. Each gate can independently control access to specific memory instances from specific logic endpoints, breaking down the complex arbitration logic into manageable segments that can be tested individually through the true data path.
Solution Approach 2:
The patent applies local quality by allowing different regions of the memory interface to have different access characteristics during testing. The path selector and gating circuits enable specific memory instances to be accessed by specific logic endpoints based on test requirements, rather than applying uniform access rules across the entire interface.
3Reliability
If the true data path through functional interface is tested, then fault detection coverage is improved, but test control complexity increases
Solution Approach 1:
The test override circuit provides multi-functionality by serving both functional operation and testing purposes. The same path selector and gating circuitry that control data flow during normal operation are reused during testing, eliminating the need for separate dedicated test control logic and reducing overall test control complexity.
Solution Approach 2:
The memory interface testing system performs self-service by utilizing its own existing control structures (path selector, gates) to enable testing. The functional interface components themselves are repurposed to control the test patterns through the true data path, rather than requiring entirely external test control mechanisms.
Data Source
AI summary
A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.