ATE Test Flow Scheduling for Semiconductor Failure Detection
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Solution Overview
Problem
The existing automated test equipment (ATE) processes for semiconductor chips are inefficient in detecting defects, as they require a fixed and pre-determined test flow that does not account for real-time variations or dependencies between tests, leading to prolonged detection times.
Innovation Solution
A computer-implemented system that optimizes the test flow within ATE stations by determining and scheduling test blocks using independent and dependent failure models, which order tests to minimize the time to detect failures, while respecting test process constraints and utilizing historical data for dynamic real-time updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a fixed and pre-determined test flow is used in ATE, then the test process is simple to implement, but the mean time to detect failure is prolonged
Solution Approach 1:
The patent implements dynamic test flow scheduling that adapts to real-time test outcomes and historical data. The system continuously updates the test sequence based on observed failure patterns and dependencies, transforming the static fixed test flow into a dynamic adaptive process that optimizes failure detection time while managing complexity through automated decision-making algorithms
Solution Approach 2:
The system incorporates feedback mechanisms by analyzing historical test data and real-time outcomes to continuously refine the test flow scheduling. The feedback loop uses observed failure patterns and test dependencies to adjust the test sequence, enabling the system to learn from past performance and optimize future scheduling decisions without manual intervention
2Manufacturing precision
If comprehensive electrical, functional and characterization tests are performed on all semiconductor chips, then the yield determination is accurate, but the end-to-end test process consumes significant time
Solution Approach 1:
The patent segments the comprehensive test process into distinct electrical, functional, and characterization test phases. By dividing the test flow into manageable segments and scheduling them optimally based on failure detection priorities, the system maintains comprehensive testing coverage while reducing overall test time through parallel processing and intelligent sequencing of test segments
Solution Approach 2:
The system applies partial action by performing only the necessary subset of tests required to detect failures and determine yield, rather than uniformly applying all comprehensive tests to every chip. The optimized scheduling identifies and executes critical test sequences that provide sufficient information for accurate yield determination while minimizing redundant testing
Data Source
AI summary
The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.