ATM Device Bandwidth Allocation via Virtual Circuit Credits

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Solution Overview

Problem

Asynchronous transfer mode (ATM) networks face challenges in efficiently sharing line bandwidth among virtual circuits while meeting priority requirements and supporting over-subscription, where the aggregate allocated bandwidth exceeds the line bandwidth.

Innovation Solution

Implementing an ATM device that uses counters to manage bandwidth allocation and prioritize cell transmission based on virtual circuit types (CBR, VBR, VBR-RT, VBR-nRT, and UBR) by ensuring cells are transmitted only when their allocated bandwidth is available, and enforcing ATM standards for priority and peak cell rate constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If over-subscription is implemented (aggregate allocated bandwidth exceeds line bandwidth), then bandwidth utilization and network capacity are improved, but bandwidth allocation control and QoS guarantee become difficult to maintain

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidbandwidth allocation control
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing credit values for each virtual circuit based on their allocated bandwidth and traffic patterns. These credit values are computed in advance and stored in memory, allowing the scheduler to make immediate transmission decisions without complex real-time calculations when over-subscription occurs, thus maintaining control reliability while enabling high bandwidth utilization

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces credit values as an intermediary mechanism between bandwidth allocation and cell transmission. Instead of directly managing bandwidth shares among over-subscribed virtual circuits, the system uses credit values (stored in memory) as a mediator that translates allocated bandwidth into transmission opportunities, simplifying the control mechanism while supporting over-subscription

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If priority scheduling is implemented for different virtual circuit types, then QoS requirements are met, but transmission delay for lower-priority circuits increases

Engineering Contradiction:
ImproveQoS guaranteeVSAvoidtransmission delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic action by using credit-based scheduling where each virtual circuit accumulates credits periodically based on its allocated bandwidth. When credits are sufficient, cells are transmitted; when not, transmission is deferred. This periodic credit accumulation mechanism ensures that lower-priority circuits eventually get transmission opportunities, reducing their delay while maintaining QoS for higher-priority circuits

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies dynamics by making the transmission schedule adaptive rather than static. The credit values and scheduling decisions are dynamically adjusted based on current buffer status, traffic patterns, and priority levels. This dynamic approach allows the system to optimize the balance between QoS guarantee and transmission delay in real-time

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7477603B1Sharing line bandwidth among virtual circuits in an ATM device
Publication Date: 2009.01.13 CISCO TECHNOLOGY INC
  • US7477603B1 patent drawing
  • US7477603B1 patent drawing
  • US7477603B1 patent drawing

AI summary

Support for over-subscription while maintaining priorities (e.g., CBR, VBR RT, VBR nRT, UBR, in that order from high to low) and ensuring that each virtual circuit does not exceed any allocated bandwidth. In an embodiment, a line slot credit is maintained associated with each virtual circuit, which is incremented by a token value (equivalent to a cell slot for transmission on the communication path) in each cell slot. When the line slot credit equals or exceeds a inter-cell delay for the virtual circuit, a VC-credit associated with the virtual circuit is incremented unless the VC-credit value would exceed any maximum threshold value. Cells are transmitted (for VC-types with allocated bandwidths) if the associated VC-credit is at least one, while maintaining priorities by VC-type. PCR may also be enforced on VBR and UBR VC-types.