ATM Synchronous Clock Supply Fault Rerouting
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Solution Overview
Problem
Conventional synchronous clock supply systems in ATM networks fail to maintain high-precision synchronization when a fault occurs in the clock supply route, leading to disconnection of nodes from the clocked network, as they cannot switch to an alternative clock source efficiently.
Innovation Solution
A synchronous clock supply system with relay nodes and a termination node that detects faults, sends fault notification data, and switches clock supply ports to maintain synchronization by rerouting the clock through alternative virtual paths, ensuring all nodes receive an identical synchronous clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock supply route is used to maintain simple network structure, then device complexity is reduced, but reliability deteriorates when a fault occurs in the clock supply route
Solution Approach 1:
The patent establishes multiple predetermined clock supply routes before any fault occurs. When a fault is detected in the current clock supply route, the system can immediately switch to an alternative predetermined route without requiring complex real-time path calculation or reconstruction, thus maintaining reliability while keeping the overall system structure relatively simple.
Solution Approach 2:
The system changes the operational state of the network by switching between different clock supply routes based on fault conditions. This parameter change (route selection) allows the system to adapt to failures while maintaining a relatively stable overall network architecture.
2Reliability
If multiple clock supply sources are used to improve reliability during faults, then clock supply continuity is improved, but manufacturing precision deteriorates due to inability to supply identical synchronous clock
Solution Approach 1:
The patent uses a clock synchronization device as an intermediary between different clock sources and the network. This intermediary device receives clocks from multiple potential sources, synchronizes them, and ensures that identical synchronous clocks are supplied to all network portions regardless of which physical source is being used, thus maintaining both reliability and synchronization precision.
Solution Approach 2:
The system separates the clock supply function into distinct segments: clock sources, clock synchronization devices, and clock distribution network. This segmentation allows different clock sources to be used for reliability while the synchronization device ensures precision by standardizing the clock signal before distribution.
3Adaptability or versatility
If conventional fault tolerance techniques are used to cope with line faults, then adaptability is improved, but manufacturing precision deteriorates due to inability to maintain identical synchronous clock supply
Solution Approach 1:
The clock synchronization device acts as a mediator that receives clocks from different sources depending on fault conditions, synchronizes them, and ensures identical synchronous clock supply to the network. This intermediary function provides both fault adaptability and synchronization precision simultaneously.
Solution Approach 2:
The system implements feedback mechanisms where clock synchronization devices monitor the status of clock supply routes and automatically adjust by selecting alternative routes or sources while maintaining synchronization precision through continuous monitoring and adjustment.
Data Source
AI summary
A switching unit (1011) receives video data (103) sent from a device (102), and sends an ATM cell synchronized with the clock to switching units (1012-1014) by a signal (including optical data) containing a frequency component serving as a synchronous clock supply source. If a fault occurs midway along a line, the switching unit (1012) which detects the fault sends an AIS cell to an OAM connection (109). The termination switching unit (1014) switches a port f for receiving a synchronous clock to a port g, and sends back an RDI cell. The switching units (1013, 1012) which have received the RDI cell switch the synchronous clock to ports e and c and receive it, thus obtaining an identical clock.