ATM Display Dual-Processor Segmentation for High-Speed Video
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Solution Overview
Problem
Electronic payment terminals are limited in displaying images due to security constraints, which restrict the data transmission rate, resulting in only simple alphanumeric messages being displayed, as the security processor is not suited for high-rate data transmission to the display screen.
Innovation Solution
An electronic payment terminal is designed with two processors: a security processor for low-rate data transmission and an application processor for high-rate data transmission, allowing the display screen to receive data through separate terminals and a selection signal to control which data is displayed, enabling the display of high-speed images while maintaining security compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the security processor is used to transmit data to the display screen, then security constraints are satisfied, but the data transmission rate is limited to low speed
Solution Approach 1:
The display data input is segmented into two separate terminals: a first terminal connected to the security processor for receiving low-rate data, and a second terminal for receiving high-rate data. This segmentation allows each processor to operate at its optimal speed while maintaining security requirements.
Solution Approach 2:
A selection signal mechanism acts as an intermediary between the two data sources and the display screen. The selection signal chooses which data source (first or second terminal) is active at any given time, enabling the system to switch between secure low-rate display and high-rate image display as needed.
2Adaptability or versatility
If the display screen is used for displaying simple messages, then security processor compatibility is maintained, but the display capability is limited
Solution Approach 1:
The display screen is designed with universal input capability to accept both low-rate data from the security processor and high-rate data from the second terminal. This multi-functionality allows the same display hardware to serve both security-critical applications and high-performance image display needs.
Solution Approach 2:
The system dynamically switches between different data sources based on operational needs. The selection signal can be changed in real-time to switch between the security processor's low-rate output and the second terminal's high-rate output, making the display capability adaptable to different operational modes.
3Speed
If the security processor is modified to transmit data at high rate, then display performance improves, but security constraints may be compromised and design complexity increases
Solution Approach 1:
The high-rate data transmission capability is extracted from the security processor and placed in a separate second terminal. This extraction allows the security processor to maintain its security-critical functions at low data rates while the system gains high-rate display capability through the separate terminal.
Solution Approach 2:
The data transmission path is segmented into two independent channels: one through the security processor for secure low-rate communication, and another through the second terminal for high-rate image data. This segmentation preserves security requirements while enabling high-performance display.
Data Source
Figure 1~2
AI summary
The invention relates to an electronic payment terminal (10) including a display screen (12) including first and second terminals (22, 24) for receiving display data, a first processor (14) connected to the first terminal (24) and adapted for supplying display data to the first terminal at a first rate, and a second processor (13) connected to the second terminal (22) and adapted for supplying display data to the second terminal at a second rate lower than the first rate and adapted for supplying to the display screen a signal for the selection of the display data received at one of the first and second terminals. The second processor (13) is further connected to the first processor (14) and is adapted to send to the first processor a signal for authorising or forbidding the transmission of display data to the display screen (12).