Atomic Context Switching With Temporary Memory Map Isolation
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Solution Overview
Problem
Existing context switching methods in data processing apparatuses require wholesale translation disabling and cache maintenance operations, leading to delays and lack of time determinism, particularly in real-time processing.
Innovation Solution
A method for context switching that selectively disables memory region definitions, copies required definitions to spare registers, and atomically switches to a temporary context using all-cacheable attributes, avoiding wholesale translation disabling and cache maintenance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wholesale translation disabling and cache maintenance operations are performed during context switching, then memory access control and process isolation are ensured, but context switch delays increase and time determinism is lost
Solution Approach 1:
The patent segments the memory region definitions into enabled and disabled states, allowing selective translation disabling rather than wholesale disabling. The memory region definitions register is divided into multiple entries, where only the entries not required for the routine are disabled, while others remain enabled to maintain necessary memory access control during context switching.
Solution Approach 2:
The patent performs preliminary actions by copying required memory region definitions to spare elements before the actual context switch. This preparation allows the new context to have its memory map already configured without requiring cache maintenance operations, eliminating the time penalty while ensuring proper memory access control.
2Reliability
If wholesale translation disabling is performed during context switching, then process isolation is maintained, but time determinism is lost
Solution Approach 1:
The patent applies local quality by selectively disabling only those memory region definitions that are not required for the routine execution. This localized approach maintains process isolation for unaffected regions while preserving necessary memory access capabilities for the routine, thereby maintaining time determinism without compromising isolation integrity.
Solution Approach 2:
The patent copies required memory region definitions to spare elements in the register before context switching. This copying mechanism ensures that the new context receives a complete and accurate memory map without requiring cache maintenance, maintaining both process isolation and time determinism simultaneously.
3Reliability
If cache maintenance operations are performed during context switching, then memory consistency is ensured, but context switch performance decreases
Solution Approach 1:
The patent extracts the cache maintenance requirement from the context switching process by using a specialized memory region definitions register that stores translation information independently of the cache. This extraction allows context switching to proceed without cache maintenance operations, maintaining memory consistency through the register-based translation mechanism while significantly improving context switch performance.
Solution Approach 2:
The patent introduces the memory region definitions register as an intermediary between the memory access control system and the context switching mechanism. This intermediary stores translation information that can be rapidly switched between contexts without requiring cache maintenance, ensuring memory consistency while eliminating the performance penalty associated with traditional cache maintenance operations.
Data Source
AI summary
Methods of context switching, and corresponding computer programs, storage media, and apparatuses are disclosed. Data processing operations are performed in a first context and a routine is called which is to be executed in a second context. Initially the routine executes in the first context. Then memory region definitions other than those required for execution of the routine are disabled. A temporary switch is made to a set of all-cacheable memory access attributes. Then memory region definitions required for execution of the routine are copied into one or more spare elements of a memory region definitions register. An atomic switch of execution of the routine to a temporary context using a temporary memory map is carried out, by enabling the copy of the one or more memory region definitions required for execution of the routine and disabling the original versions. Then a second memory map is set up by storing a second set of memory region definitions in one or more predetermined elements of the memory region definitions register. Finally another atomic switch is carried out, switching execution of the routine to the second context using the second memory map by enabling new second set of memory region definitions and disabling the temporary copies of the memory region definitions.